IP Library Granted Patent US 11,049,871
Granted Patent B2
US 11,049,871 · App. 16/558,654 · Granted Jun 29, 2021

Semiconductor storage device and manufacturing method of semiconductor storage device

Inventor: Ryota Ohnuki (Yokkaichi, JP)
Assignee: TOSHIBA MEMORY CORPORATION
H01L27/11578H01L27/11519H01L27/11551H01L27/11565
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Quick Facts
Patent No.
US 11,049,871
App. No.
16/558,654
Granted
Jun 29, 2021
Kind
B2
Abstract

A semiconductor storage device of an embodiment includes a plurality of pillars extending in a predetermined direction, a plurality of first memory cells arrayed on a side surface on one side of each of the pillars along an extending direction of the pillars, a plurality of second memory cells arrayed on a side surface of on another side each of the pillars along the extending direction of the pillars, a plurality of first and second word lines arrayed in the extending direction of the pillars, and respectively connected to the first and second memory cells, and in a cell array in which the plurality of pillars is disposed, the plurality of pillars are periodically arrayed without interruption in a lead-out direction of the first word lines and the second word lines.

Claims (16)

1. A manufacturing method of a semiconductor storage device, the manufacturing method comprising:

forming a stack in which a plurality of first insulating layers and a plurality of first sacrificial layers are alternately stacked;

forming a memory hole penetrating through the stack;

filling the memory hole with a second sacrificial layer;

forming a groove penetrating the stack so as to divide the stack to a first stack and a second stack, at a position intersecting with substantially a center of the memory hole filled with the second sacrificial layer, the groove having a smaller width than a diameter of the memory hole,

replacing the first sacrificial layer of the stack with a conductive layer so as to form a plurality of word lines; and

filling the memory hole with a memory layer, and forming a pillar having a plurality of first memory cells to be arrayed on a side surface of the pillar facing the first stack and a plurality of second memory cells to be arrayed on a side surface of the pillar facing the second stack.

2. The manufacturing method of a semiconductor storage device according to claim 1 , wherein, at the forming of the groove, the second sacrificial layer is left in the groove.

3. The manufacturing method of a semiconductor storage device according to claim 2 , wherein, at the forming of the groove, stacks are bridged by the second sacrificial layer.

4. The manufacturing method of a semiconductor storage device according to claim 3 , wherein

the memory hole includes a plurality of memory holes, and

at the forming of the plurality of memory hole, in a cell array formation planned region, the plurality of memory holes are periodically formed without interruption in a predetermined direction.

5. The manufacturing method of a semiconductor storage device according to claim 4 , wherein, at the forming of the groove, in the cell array formation planned region, the groove is formed so as to extend continuously in a direction in which the memory holes are arrayed.

6. The manufacturing method of a semiconductor storage device according to claim 4 , wherein, at the forming of the plurality of memory holes, each memory hole of the plurality of memory holes is formed in such a manner that an opened surface of the memory hole has an ellipse or oval shape having a long diameter in a direction intersecting with the predetermined direction, and a ratio of a long diameter of an end surface of the memory hole with respect to a short diameter of the end surface of the memory hole becomes larger than 1.

7. The manufacturing method of a semiconductor storage device according to claim 2 , wherein, at the forming of the groove, the groove is formed in a state in which an end surface of the memory hole is covered with the second sacrificial layer.

8. The manufacturing method of a semiconductor storage device according to claim 1 , the manufacturing method further comprising filling the groove with a second insulating layer, and forming a separation layer separating the stack.

Assignments (2)
CHANGE OF NAME AND ADDRESS Recorded Jan 31, 2022
From: TOSHIBA MEMORY CORPORATION
To: KIOXIA CORPORATION
Reel/Frame 058905/0582 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 3, 2019
From: OHNUKI, RYOTA
To: TOSHIBA MEMORY CORPORATION
Reel/Frame 050248/0023 →