Receiving apparatus and method

1. A receiving device, comprising:

a first circuit configured to calculate a phase difference between a first clock signal and a data signal modulated by pulse-amplitude modulation;

a second circuit configured to generate a second clock signal based on the first clock signal and the phase difference, and to add jitter to the second clock signal;

a third circuit configured to demodulate the data signal by comparing an amplitude of each pulse of the data signal with a threshold value at a timing synchronized to the second clock signal added the jitter; and

a processing circuit configured to count a number of errors in the demodulated data signal and calibrate the threshold value based on the counted number of errors.

2. The receiving device according to claim 1 , wherein the processing circuit is further configured to adjust the threshold value, clear the counted number of errors, and repeat the demodulation of the data signal with the adjusted threshold value if a data size of the demodulated data signal reaches a particular size.

3. The receiving device according to claim 2 , wherein the processing circuit is further configured to select the threshold value from a plurality of candidate threshold values.

4. The receiving device according to claim 3 , wherein the processing circuit is further configured to reduce an amplitude of the jitter when the plurality of candidate threshold values do not include any candidate that satisfies a predetermined criterion, and repeat the demodulation of the data signal with reduced jitter.

5. The receiving device according to claim 2 , wherein the processing circuit is further configured to adjust the threshold value, clear the counted number of errors, and repeat the demodulation of the data signal with the adjusted threshold value if the counted number of errors reaches a predetermined value before the data size has reached the predetermined size.

6. The receiving device according to claim 1 , wherein the data signal includes a plurality of bits of data per symbol.

7. The receiving device according to claim 1 , wherein

the processing circuit is further configured to generate a jitter generation signal, and

the second circuit is configured to add jitter, to the first clock signal, having an amplitude being set based on the jitter generation signal.

8. The receiving device according to claim 7 , wherein

the first circuit is configured to generate an adjustment signal based on the phase difference calculated, and

the second circuit is configured to adjust the phase difference based on the adjustment signal generated by the first circuit.

9. The receiving device according to claim 8 , wherein the second circuit is configured to add a first value corresponding to the jitter generation signal to a second value corresponding to the adjustment signal, and adjust a phase of the second clock signal based on a third value corresponding to an addition of the first value and the second value.

10. The receiving device according to claim 1 , wherein the jitter has a frequency that is higher than a response band of the first circuit.

11. A method of signal demodulation, the method comprising:

calculating a phase difference between a first clock signal and a data signal modulated by pulse-amplitude modulation;

generating a second clock signal based on the first clock signal and the calculated phase difference, and adding jitter to the second clock signal added the jitter;

demodulating the data signal by comparing an amplitude of each pulse of the data signal with a threshold value at a timing synchronized to the second clock signal;

counting a number of errors in the demodulated data signal; and

performing calibration of the threshold value based on the counted number of errors.

12. The method according to claim 11 , wherein the calibration comprises:

adjusting the threshold value, clearing the counted number of errors, and repeating the demodulation of the data signal with the adjusted threshold value if a data size of the demodulated data signal reaches a particular size.

13. The method according to claim 12 , wherein the calibration further comprises:

selecting the threshold value from a plurality of candidate threshold values.

14. The method according to claim 13 , wherein the calibration further comprises:

reducing an amplitude of the jitter when the plurality of candidate threshold values do not include any candidate that satisfies a predetermined criterion; and

repeating the demodulation of the data signal with reduced jitter.

15. The method according to claim 12 , wherein the calibration further comprises:

adjusting the threshold value, clearing the counted number of errors, and repeating the demodulation of the data signal with the adjusted threshold value if the counted number of errors reaches a predetermined value before the data size has reached the predetermined size.

16. The method according to claim 11 , wherein the data signal includes a plurality of bits of data per symbol.

17. The method according to claim 11 , further comprising:

generating a jitter generation signal; and

adding jitter, to the first clock signal, having an amplitude being based on the jitter generation signal.

18. The method according to claim 17 , further comprising:

generating an adjustment signal based on the calculated phase difference; and

adjusting the phase difference based on the adjustment signal.

19. The method according to claim 18 , further comprising:

adding a first value corresponding to the jitter generation signal to a second value corresponding to the adjustment signal; and

adjusting a phase of the second clock signal based on a third value corresponding to an addition of the first value and the second value.

20. The method according to claim 11 , wherein the jitter has a frequency that is higher than a response band of the calculating the phase difference.