Memory system and method
According to an embodiment, a memory system includes a plurality of memory cells and a memory controller. The memory controller executes a read operation on the plurality of memory cells using one or more reference read voltages to acquire a histogram representing the number of memory cells with respect to a threshold voltage. The memory controller inputs the histogram to a trained neural network model including an output layer for outputting one or more actual read voltages to read data from the memory cells. The memory controller executes a read operation on the memory cells using the one or more actual read voltages output from the output layer.
1. A memory system comprising:
a plurality of memory cells; and
a memory controller that:
executes a read operation on a plurality of memory cells using one or more reference read voltages to acquire a histogram representing a number of memory cells with respect to a threshold voltage,
inputs the histogram to a trained neural network model, the trained neural network model comprising an output layer for outputting one or more actual read voltages to read data from the plurality of memory cells, and
executes a read operation on the plurality of memory cells using the one or more actual read voltages output from the output layer.
2. The memory system according to claim 1 , wherein
the neural network model comprising an input layer including a first node and a second node, and
the memory controller inputs the histogram to the first node and inputs property information to the second node.
3. The memory system according to claim 2 , wherein
the neural network model further comprises one or more hidden layers, and
the one or more hidden layers include a third node to be activated by a non-linear activation function.
4. The memory system according to claim 2 , wherein
the property information includes the number of executed program/erase cycles to the plurality of memory cells.
5. The memory system according to claim 2 , wherein
the property information includes the number of executed read operations to the plurality of memory cells.
6. The memory system according to claim 2 , wherein
the property information includes location information of the plurality of memory cells.
7. The memory system according to claim 2 , further comprising
a temperature sensor, wherein
the property information includes an output value of the temperature sensor.
8. The memory system according to claim 2 , wherein
the property information includes an elapsed time after a program operation is executed on the plurality of memory cells.
9. The memory system according to claim 1 , wherein
the number of the reference read voltages is smaller than the number of the actual read voltages.
10. A method for controlling a non-volatile memory comprising a plurality of memory cells, the method comprising:
executing a read operation on the plurality of memory cells using one or more reference read voltages;
acquiring, by the read operation, a histogram representing a number of memory cells with respect to a threshold voltage;
inputting the histogram to a trained neural network model, the trained neural network model comprising an output layer for outputting one or more actual read voltages to read data from the plurality of memory cells; and
executing a read operation on the plurality of memory cells using the one or more actual read voltages output from the output layer.
11. The method according to claim 10 , further comprising:
acquiring property information; and
inputting the properly information to the trained neural network model.
12. The method according to claim 11 , wherein
the neural network model includes one or more hidden layers, and
the one or more hidden layers include a node to be activated by a non-linear activation function.
13. The method according to claim 11 , wherein
the property information includes the number of executed program/erase cycles to the plurality of memory cells.
14. The method according to claim 11 , wherein
the property information includes the number of executed read operations to the plurality of memory cells.
15. The method according to claim 11 , wherein
the property information includes location information of the plurality of memory cells.
16. The method according to claim 11 , wherein
the property information includes an output value of a temperature sensor.
17. The method according to claim 11 , wherein
the property information includes an elapsed time after a program operation is executed on the plurality of memory cells.
18. The method according to claim 10 , wherein
the number of the reference read voltages is smaller than the number of the actual read voltages.