Semiconductor memory device in which memory cells are three-dimensionally arrange
A semiconductor memory device includes a first block and a second block arranged adjacent to each other in a Y direction. Each of the first and second blocks includes conductive layers extended in an X direction, memory trenches between the conductive layers, memory pillars provided across two conductive layers with a memory trench interposed therebetween, and transistors provided between the memory pillars and the conductive layers. One of the conductive layers provided at an end of the first block in the Y direction is electrically connected to one of the conductive layers provided at an end of the second block.
1. A semiconductor memory device comprising:
a first block and a second block each including a plurality of memory cell transistors and arranged adjacent to each other in a first direction,
wherein each of the first and second blocks includes:
a plurality of first conductive layers that extend in a second direction orthogonal to the first direction and are arranged relative to each other along the first direction;
a plurality of first insulating layers that are provided between the first conductive layers and extend in a third direction orthogonal to both of the first and second directions;
a plurality of first pillars that are provided across two of the plurality of first conductive layers with one of the plurality of first insulating layers interposed therebetween, extend in the third direction, and are arranged relative to each other along the second direction; and
a plurality of first transistors that are provided by the plurality of first pillars and the plurality of first conductive layers, and wherein
at least a first one of the plurality of first conductive layers provided at an end of the first block in the first direction is electrically connected to at least a second one of the plurality of first conductive layers provided at an end of the second block in the first direction.
2. The semiconductor memory device according to claim 1 , further comprising:
a second insulating layer that is provided between the at least first one of the first conductive layers and the at least second one of the first conductive layers, and extends in the third direction, in a boundary region of the first and second blocks.
3. The semiconductor memory device according to claim 1 , further comprising:
a plurality of bit lines that are connected to the plurality of first pillars, respectively, and extend in the first direction;
a second insulating layer that is provided between the at least first one of the first conductive layers and the at least second one of the first conductive layers, and extends in the third direction, in a boundary region of the first and second blocks; and
a plurality of second pillars that are provided across two of the plurality of first conductive layers with a second insulating layer interposed therebetween, extend in the third direction, and are arranged relative to each other along the second direction such that the second pillars are not connected to the bit lines.
4. The semiconductor memory device according to claim 1 , further comprising:
a plurality of second conductive layers that extend in the second direction, are provided between the first conductive layers, and are arranged relative to each other along the first direction; and
a plurality of second transistors provided by the first pillars and the second conductive layers.
5. The semiconductor memory device according to claim 1 , wherein the plurality of first transistors include the plurality of memory cell transistors provided in the third direction, and a plurality of select transistors connected to the plurality of memory cell transistors, and
the first conductive layers are connected to gates of the select transistors.
6. The semiconductor memory device according to claim 1 , wherein the two first conductive layers, with the first insulating layer interposed therebetween, are connected to each other at one end or the other end in the second direction while another one of the plurality of first conductive layers is interposed between the two first conductive layers.
7. The semiconductor memory device according to claim 1 , wherein a page which is at least one of a write unit or a read unit is configured by a sum of one or more of the memory cell transistors in the first pillars that intersect with the first conductive layer provided at one end of the first block in the first direction, and one or more of the memory cell transistors in the first pillars that intersect with the first conductive layer provided at the other end of the first block in the first direction.
8. The semiconductor memory device according to claim 3 , wherein either one-side ends or the other-side ends of the second pillars are not electrically connected to a wire layer.
9. The semiconductor memory device according to claim 3 , wherein one or more of the memory cell transistors in the second pillars are not used for a write operation.
10. The semiconductor memory device according to claim 1 , wherein each of the first and second blocks is a unit in which data stored in the memory cell transistors is collectively erased in which data stored in the memory cell transistors is erased.