Semiconductor memory device

1. A semiconductor memory device, comprising:

a memory cell; and

a control circuit configured to:

charge a first node to a first voltage, the first voltage being based on an electric resistance of the memory cell when first data is stored in the memory cell;

write second data to the memory cell after the first node is charged to the first voltage;

charge a second node to a second voltage, the second voltage being based on an electric resistance of the memory cell when the second data is stored in the memory cell; and

determine, based on the first voltage and the second voltage, whether or not the first data is different from the second data,

wherein the control circuit includes:

a first switching element including a first end electrically coupled to the first node, and a second end electrically coupled to a third node between the first node and the second node;

a second switching element including a first end and a second end that are electrically coupled to the first node; and

a third switching element including a first end electrically coupled to the second node and a second end electrically coupled to the third node,

wherein the control circuit is configured to switch the second switching element to an ON state on or after switching the first switching element to an OFF state.

2. The device of claim 1 , wherein the second switching element is equal in capacitance to the first switching element.

3. The device of claim 1 , wherein the control circuit is configured to switch the second switching element to the ON state before starting to charge the second node based on the second data.

4. The device of claim 1 , wherein the control circuit is configured to switch the second switching element to the ON state after starting to charge the second node based on the second data.

5. The device of claim 1 , wherein:

the control circuit further includes a fourth switching element electrically coupled in parallel to the first switching element between the first node and the third node; and

the first switching element and the second switching element are smaller in capacitance than the fourth switching element.

6. The device of claim 5 , wherein the second switching element is equal in capacitance to the first switching element.

7. The device of claim 5 , wherein the control circuit is configured to switch the first switching element to the OFF state after switching the fourth switching element to an OFF state.

8. The device of claim 1 , wherein:

the control circuit further includes:

a fourth switching element electrically coupled in parallel to the first switching element between the first node and the third node; and

a fifth switching element including a first end and a second end that are electrically coupled to the first node; and

the first switching element and the second switching element are smaller in capacitance than the fourth switching element and the fifth switching element.

9. The device of claim 8 , wherein:

the second switching element is equal in capacitance to the first switching element; and

the fifth switching element is equal in capacitance to the fourth switching element.

10. The device of claim 8 , further comprising a monitor circuit configured to monitor the semiconductor memory device,

wherein the control circuit is configured to:

when a monitor result of the monitor circuit meets a condition, switch the first switching element to the OFF state after switching the fourth switching element to an OFF state, and switch the second switching element to the ON state on or after switching the first switching element to the OFF state and before starting to charge the second node based on the second data; and

when the monitor result of the monitor circuit does not meet the condition, switch the fourth switching element to the OFF state before switching the first switching element to the OFF state, and switch the second switching element to the ON state on or after switching the first switching element to the OFF state and after starting to charge the second node based on the second data.

11. The device of claim 10 , wherein:

the monitor result includes a voltage of the third node; and

meeting the condition includes the voltage of the third node being equal to or larger than a predetermined value.

12. The device of claim 10 , wherein:

the monitor result includes a temperature; and

meeting the condition includes the temperature exceeding a threshold value.

13. The device of claim 10 , wherein:

the control circuit further includes a first transistor and a second transistor that are different in polarity;

the monitor result includes a first capacitance of the first transistor and a second capacitance of the second transistor; and

meeting the condition includes the first capacitance being larger than the second capacitance.

14. The device of claim 13 , wherein:

the first switching element includes the first transistor and the second transistor; and

the first transistor and the second transistor are electrically coupled together in parallel between the first node and the third node.

15. The device of claim 1 , wherein the control circuit further includes a sixth switching element including a first end electrically coupled to the third node, a grounded second end, and a gate electrically coupled to the first node.

16. The device of claim 1 , wherein the memory cell includes a resistance change element.

17. The device of claim 16 , wherein the resistance change element is a magnetoresistive effect element.