Semiconductor integrated circuit and reception device

1. A semiconductor integrated circuit comprising:

a clock generation circuit configured to generate a first clock, and

an equalizer circuit,

wherein the equalizer circuit comprises:

a summer circuit,

a correction circuit that is electrically connected to the summer circuit and configured to be supplied a second clock on the basis of the first clock,

a variable delay circuit that is electrically connected to the correction circuit and configured to change a delay amount of the second clock, and

an adjustment circuit that is electrically connected to the summer circuit, and configured to perform sampling of values in a plurality of edge periods and values in a plurality of data periods of data output from the summer circuit, and adjust a delay amount of the variable delay circuit such that timing of the second clock supplied from the variable delay circuit to the correction circuit becomes close to target timing according to a plurality of sampling results, and

wherein the adjustment circuit comprises:

an edge sampler configured to perform sampling of the values in the edge periods of the data output from the summer circuit,

a data sampler configured to perform sampling of the values in the data periods of the data output from the summer circuit, and

a delay adjustment circuit configured to adjust the delay amount of the variable delay circuit according to a sampling result by the edge sampler and a sampling result by the data sampler.

2. The semiconductor integrated circuit according to claim 1 ,

wherein the adjustment circuit is configured to determine whether the timing of the second clock is deviated in a slower direction or a faster direction from the target timing according to the sampling results, and adjust the delay amount of the variable delay circuit according to a result of the determination.

3. The semiconductor integrated circuit according to claim 2 ,

wherein the adjustment circuit is configured to decrease the delay amount of the variable delay circuit in a case where the timing of the second clock is deviated in the slower direction from the target timing, and increase the delay amount of the variable delay circuit in a case where the timing of the second clock is deviated in the faster direction from the target timing.

4. The semiconductor integrated circuit according to claim 1 ,

wherein the target timing is transition timing of a signal level of the data output from the summer circuit.

5. The semiconductor integrated circuit according to claim 1 ,

wherein the delay adjustment circuit is configured to adjust the delay amount of the variable delay circuit in a case where a combination of the sampling result by the edge sampler and the sampling result by the data sampler match a predetermined pattern.

6. The semiconductor integrated circuit according to claim 5 ,

wherein when k is an integer equal to or larger than 0, the predetermined pattern includes a (k+3)-th data sampling result, a (k+2)-th data sampling result, a (k+1)-th edge sampling result, a (k+1)-th data sampling result, a k-th edge sampling result, and a k-th data sampling result, wherein the k-th edge sampling is a timing between the (k+1)-th data sampling and the k-th data sampling, and the (k+1)-th edge sampling is a timing between the (k+2)-th data sampling and the (k+1)-th data sampling.

7. The semiconductor integrated circuit according to claim 5 ,

wherein the delay adjustment circuit is configured to adjust the delay amount of the variable delay circuit in a case where the combination matches the predetermined pattern at a particular frequency.

8. The semiconductor integrated circuit according to claim 5 , wherein the clock generation circuit is configured to generate the first clock by performing a phase adjustment with data output from the equalizer circuit and supply the first clock to the equalizer circuit,

wherein the predetermined pattern is a pattern with which the phase adjustment of the first clock is not performed in the clock generation circuit.

9. The semiconductor integrated circuit according to claim 1 ,

wherein in a case where a combination of the sampling result by the edge sampler and the sampling result by the data sampler matches a predetermined pattern, the delay adjustment circuit is configured to determine whether the timing of the second clock is deviated in a slower direction or a faster direction from the target timing and adjust the delay amount of the variable delay circuit according to a result of the determination.

10. The semiconductor integrated circuit according to claim 9 ,

wherein the delay adjustment circuit is configured to decrease the delay amount of the variable delay circuit in a case where the timing of the second clock is deviated in the slower direction from the target timing, and increase the delay amount of the variable delay circuit in a case where the timing of the second clock is deviated in the faster direction from the target timing.

11. The semiconductor integrated circuit according to claim 1 ,

wherein the delay adjustment circuit is configured to determine that the timing of the second clock is deviated in a slower direction from the target timing in a case where a combination of the sampling result by the edge sampler and the sampling result by the data sampler matches at least a first pattern, and determine that the timing of the second clock is deviated in a faster direction from the target timing in a case where the combination matches a second pattern different from the first pattern.

12. The semiconductor integrated circuit according to claim 11 ,

wherein the delay adjustment circuit is configured to decrease the delay amount of the variable delay circuit in a case where the timing of the second clock is deviated in a slower direction from the target timing, and increase the delay amount of the variable delay circuit in a case where the timing of the second clock is deviated in a faster direction from the target timing.

13. The semiconductor integrated circuit according to claim 1 ,

wherein the correction circuit further includes a first feedback node to which the sampling result by the edge sampler is fed back, and a second feedback node to which the sampling result by the data sampler is fed back.

14. The semiconductor integrated circuit according to claim 1 ,

wherein the equalizer circuit further comprises

a delay circuit that is electrically connected to the adjustment circuit, and

the adjustment circuit performs, by using a delayed clock supplied from the delay circuit, sampling of the values in the edge periods of the data output from the summer circuit.

15. The semiconductor integrated circuit according to claim 14 ,

wherein the delay circuit includes a fixed delay amount.

16. A reception device comprising: the semiconductor integrated circuit according to claim 1 ; and a circuit configured to receive data output from the semiconductor integrated circuit.

17. The reception device according to claim 16 ,

wherein the adjustment circuit is configured to determine whether the timing of the second clock is deviated in a slower direction or a faster direction from the target timing according to the sampling results, and adjust the delay amount of the variable delay circuit according to a result of the determination.

18. The reception device according to claim 16 ,

wherein the equalizer circuit further comprises

a delay circuit that is electrically connected to the adjustment circuit, and

the adjustment circuit performs, by using a delayed clock supplied from the delay circuit, sampling of the values in the edge periods of the data output from the summer circuit.