IP Library › Granted Patent US 10,861,536
Granted Patent B2
US 10,861,536 · App. 16/560,472 · Granted Dec 8, 2020

Semiconductor memory device

Inventors: Yoshihiko Kamata (Yokohama, JP); Takuyo Kodama (Sagamihara, JP); Yuki Ishizaki (Yokohama, JP); Yoko Deguchi (Yokohama, JP)
Assignee: Toshiba Memory Corporation
G11C11/5642G11C11/5671G11C16/24G11C16/26H01L27/11556H01L27/11582
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Quick Facts
Patent No.
US 10,861,536
App. No.
16/560,472
Granted
Dec 8, 2020
Kind
B2
Abstract

A semiconductor memory device includes: a first memory cell transistor; a bit line electrically connected to a first end of the first memory cell transistor; a source line electrically connected to a second end of the first memory cell transistor; and a control circuit. When a read operation for reading read data from the first memory cell transistor is performed, the control circuit is configured to apply a first voltage to the bit line in a first period, apply a second voltage, higher than the first voltage, to the bit line, and also apply a third voltage, lower than the first voltage, to the source line in a second period subsequent to the first period, and sense a threshold voltage of the first memory cell transistor in a third period subsequent to the second period.

Claims (93)

1. A semiconductor memory device comprising:

a first memory cell transistor;

a bit line electrically connected to a first end of the first memory cell transistor;

a source line electrically connected to a second end of the first memory cell transistor; and

a control circuit,

wherein

when a read operation for reading read data from the first memory cell transistor is performed, the control circuit is configured to

apply a first voltage to the bit line in a first period,

apply a second voltage, higher than the first voltage, to the bit line in a second period subsequent to the first period, and also apply a third voltage, lower than the first voltage, to the source line, in the second period subsequent to the first period, and

sense a threshold voltage of the first memory cell transistor in a third period subsequent to the second period,

wherein the control circuit is further configured to apply the first voltage to the source line in the first period, and

wherein the control circuit includes

a first driver, and

a first transistor having a first threshold voltage and including a first end electrically connected to the first end of the first memory cell transistor via the bit line, and a second end electrically connected to the first driver, and

in the first period, the control circuit is further configured to

apply a sum of the second voltage and the first threshold voltage to a gate of the first transistor, and

apply the first voltage driven by the first driver to the bit line via the first transistor.

2. The semiconductor memory device according to claim 1 , wherein

the control circuit includes

a first driver, and

a first transistor having a first threshold voltage and including a first end electrically connected to the first end of the first memory cell transistor via the bit line, and a second end electrically connected to the first driver, and

in the first period, the control circuit is further configured to

apply a sum of the first voltage and the first threshold voltage to a gate of the first transistor, and

cause the first transistor to clamp a voltage driven by the first driver to the first voltage and apply the first voltage to the bit line.

3. The semiconductor memory device according to claim 1 , further comprising:

a second transistor configured to electrically connect between the first end of the first memory cell transistor and the bit line;

a second memory cell transistor including a first end electrically connected to the bit line, a second end electrically connected to the source line, and a gate electrically connected to a word line electrically connected to a gate of the first memory cell transistor; and

a third transistor configured to electrically connect between the first end of the second memory cell transistor and the bit line,

wherein the control circuit is further configured to turn off the third transistor in the first period.

4. The semiconductor memory device according to claim 3 , further comprising:

a fourth transistor configured to electrically connect between the second end of the second memory cell transistor and the source line,

wherein the control circuit is further configured to turn on the fourth transistor in the first period.

5. The semiconductor memory device according to claim 4 , wherein the control circuit is further configured to cause the source line to be in a floating state in the first period.

6. The semiconductor memory device according to claim 5 , wherein

the control circuit includes

a first driver, and

a first transistor having a first threshold voltage and including a first end electrically connected to the first end of the first memory cell transistor via the bit line, and a second end electrically connected to the first driver, and

in the first period, the control circuit is further configured to

apply a sum of the second voltage and the first threshold voltage to a gate of the first transistor, and

apply the first voltage driven by the first driver to the bit line via the first transistor.

7. The semiconductor memory device according to claim 5 , wherein

the control circuit includes

a first driver, and

a first transistor having a first threshold voltage and including a first end electrically connected to the first end of the first memory cell transistor via the bit line, and a second end electrically connected to the first driver, and

in the first period, the control circuit is further configured to

apply a sum of the first voltage and the first threshold voltage to a gate of the first transistor, and

cause the first transistor to clamp a voltage driven by the first driver to the first voltage and apply the first voltage to the bit line.

8. The semiconductor memory device according to claim 1 , wherein

the first memory cell transistor is configured to store data of 2 bits or more, and

the control circuit is further configured to

sense the threshold voltage of the first memory cell transistor by use of a first read voltage in the third period,

apply the first voltage to the bit line in a fourth period subsequent to the third period,

apply the second voltage to the bit line and also apply the third voltage to the source line, in a fifth period subsequent to the fourth period, and

sense the threshold voltage of the first memory cell transistor by use of a second read voltage in a sixth period subsequent to the fifth period.

9. The semiconductor memory device according to claim 8 , wherein

the control circuit is further configured to apply the first voltage to the source line in the first period and the fourth period.

10. The semiconductor memory device according to claim 9 , wherein

the control circuit includes

a first driver, and

a first transistor having a first threshold voltage and including a first end electrically connected to the first end of the first memory cell transistor via the bit line, and a second end electrically connected to the first driver, and

in the first period and the fourth period, the control circuit is further configured to

apply a sum of the second voltage and the first threshold voltage to a gate of the first transistor, and

apply the first voltage driven by the first driver to the bit line via the first transistor.

11. The semiconductor memory device according to claim 9 , wherein

the control circuit includes

a first driver, and

a first transistor having a first threshold voltage and including a first end electrically connected to the first end of the first memory cell transistor via the bit line, and a second end electrically connected to the first driver, and

in the first period and the fourth period, the control circuit is further configured to

apply a sum of the first voltage and the first threshold voltage to a gate of the first transistor, and

cause the first transistor to clamp a voltage driven by the first driver to the first voltage and apply the first voltage to the bit line.

12. The semiconductor memory device according to claim 8 , further comprising:

a second transistor configured to electrically connect between the first end of the first memory cell transistor and the bit line;

a second memory cell transistor including a first end electrically connected to the bit line, a second end electrically connected to the source line, and a gate electrically connected to a word line electrically connected to a gate of the first memory cell transistor; and

a third transistor configured to electrically connect between the first end of the second memory cell transistor and the bit line, and

wherein the control circuit is further configured to turn off the third transistor in the first period and the fourth period.

13. The semiconductor memory device according to claim 12 , further comprising:

a fourth transistor configured to electrically connect between the second end of the second memory cell transistor and the source line, and

wherein the control circuit is further configured to turn on the fourth transistor in the first period and the fourth period.

14. The semiconductor memory device according to claim 13 , wherein the control circuit is further configured to cause the source line to be in a floating state in the first period and the fourth period.

15. The semiconductor memory device according to claim 14 , wherein

the control circuit includes

a first driver, and

a first transistor having a first threshold voltage and including a first end electrically connected to the first end of the first memory cell transistor via the bit line, and a second end electrically connected to the first driver, and

in the first period and the fourth period, the control circuit is further configured to:

apply a sum of the second voltage and the first threshold voltage to a gate of the first transistor; and

apply the first voltage driven by the first driver to the bit line via the first transistor.

16. The semiconductor memory device according to claim 14 , wherein

the control circuit includes

a first driver, and

a first transistor having a first threshold voltage and including a first end electrically connected to the first end of the first memory cell transistor via the bit line, and a second end electrically connected to the first driver, and

in the first period and the fourth period, the control circuit is further configured to:

apply a sum of the first voltage and the first threshold voltage to a gate of the first transistor; and

cause the first transistor to clamp a voltage driven by the first driver to the first voltage and apply the first voltage to the bit line.

Assignments (2)
CHANGE OF NAME AND ADDRESS Recorded Jan 31, 2022
From: TOSHIBA MEMORY CORPORATION
To: KIOXIA CORPORATION
Reel/Frame 058905/0582 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 4, 2019
From: KAMATA, YOSHIHIKO; KODAMA, TAKUYO; ISHIZAKI, YUKI; DEGUCHI, YOKO
To: TOSHIBA MEMORY CORPORATION
Reel/Frame 050266/0672 →