Feed-forward current compensation for CMOS signal path
An integrated circuit has a CMOS signal path coupled for receiving a data signal. A compensation circuit is coupled to a power supply rail of the CMOS signal path for injecting a compensation current into the power supply rail. The compensation circuit can be a charge pump operating in response to the data signal to inject the compensation current into the power supply rail each transition of the data signal. The compensation circuit can be a replica CMOS signal path to inject the compensation current into the power supply rail each transition of the data signal. The compensation circuit can be a voltage regulator and current mirror including an input coupled to the voltage regulator. The replica CMOS signal path receives an operating potential from the voltage regulator. An output of the current mirror injects the compensation current into the power supply rail each transition of the data signal.
1. An integrated circuit, comprising:
a CMOS signal path coupled for receiving a data signal, wherein the CMOS signal path receives an operating potential from a power supply rail; and
a compensation circuit coupled to the power supply rail for injecting a compensation current into the power supply rail each transition of the data signal, wherein the compensation circuit includes a replica CMOS signal path to inject the compensation current into the power supply rail each transition of the data signal.
2. The integrated circuit of claim 1 , wherein the replica CMOS signal path is stacked on the supply rail of the CMOS signal path to inject the compensation current into the power supply rail each transition of the data signal.
3. The integrated circuit of claim 1 , wherein the compensation circuit further includes:
a voltage regulator;
a current mirror including an input coupled to the voltage regulator; and
the replica CMOS signal path receiving an operating potential from the voltage regulator, wherein an output of the current mirror injects the compensation current into the power supply rail each transition of the data signal.
4. The integrated circuit of claim 3 , wherein the current mirror includes 1:n ratio.
5. An integrated circuit, comprising:
a CMOS signal path coupled for receiving a data signal; and
a compensation circuit coupled to a power supply rail of the CMOS signal path for injecting a compensation current into the power supply rail, wherein the compensation circuit includes a replica CMOS signal path to inject the compensation current into the power supply rail each transition of the data signal.
6. The integrated circuit of claim 5 , wherein the compensation circuit includes a level shifter coupled between the data signal and the replica CMOS signal path.
7. The integrated circuit of claim 5 , wherein the compensation circuit further includes:
a voltage regulator;
a current mirror including an input coupled to the voltage regulator; and
the replica CMOS signal path receiving an operating potential from the voltage regulator, wherein an output of the current mirror injects the compensation current into the power supply rail each transition of the data signal.
8. The integrated circuit of claim 7 , wherein the current mirror includes 1:n ratio.
9. The integrated circuit of claim 5 , wherein the CMOS signal path includes:
an inverter or buffer receiving the data signal; and
a voltage regulator providing an operating potential to the power supply rail.
10. A method of making an integrated circuit, comprising:
providing a CMOS signal path coupled for receiving a data signal; and
providing a compensation circuit coupled to a power supply rail of the CMOS signal path for injecting a compensation current into the power supply rail, wherein providing the compensation circuit includes providing a replica CMOS signal path to inject the compensation current into the power supply rail each transition of the data signal.
11. The method of claim 10 , wherein providing the compensation circuit includes providing a level shifter between the data signal and the replica CMOS signal path.
12. The method of claim 10 , wherein providing the compensation circuit further includes:
providing a voltage regulator;
providing a current mirror including an input coupled to the voltage regulator; and
providing the replica CMOS signal path receiving an operating potential from the voltage regulator, wherein an output of the current mirror injects the compensation current into the power supply rail each transition of the data signal.
13. The method of claim 12 , wherein the current mirror includes 1:n ratio.
14. The method of claim 10 , wherein providing the CMOS signal path includes:
providing an inverter or buffer receiving the data signal; and
providing a voltage regulator providing an operating potential to the power supply rail.