Semiconductor storage device
According to one embodiment, a semiconductor storage device includes a first wiring, a first resistance change element which is connected to the first wiring, a first nonlinear element which is connected to the first resistance change element, and a second wiring which is connected to the first nonlinear element. In a read operation for the first resistance change element, a voltage between the first wiring and the second wiring increases to a first voltage, and after the voltage between the first wiring and the second wiring increases to the first voltage, the voltage between the first wiring and the second wiring increases to a second voltage which is larger than the first voltage.
1. A semiconductor storage device, comprising:
a first wiring;
a first resistance change element connected to the first wiring;
a first nonlinear element connected to the first resistance change element; and
a second wiring connected to the first nonlinear element, wherein
the semiconductor storage device is configured such that in a read operation for the first resistance change element,
a voltage, applied to the semiconductor storage device through the first wiring and the second wiring, is increased to a first voltage determined based on a histogram of read threshold voltages of a plurality of memory cells in the semiconductor storage device, and
after the voltage applied through the first wiring and the second wiring is increased to the first voltage, the voltage applied through the first wiring and the second wiring is increased to a second voltage which is greater than the first voltage and determined based on the histogram.
2. The semiconductor storage device according to claim 1 , further comprising:
a third wiring;
a second resistance change element connected to the third wiring;
a second nonlinear element connected to the second resistance change element; and
a fourth wiring connected to the second nonlinear element, wherein
the semiconductor storage device is configured such that in a read operation for the second resistance change element,
a voltage, applied to the semiconductor storage device through the third wiring and the fourth wiring, is increased to the first voltage, and
after the voltage applied through the third wiring and the fourth wiring is increased to the first voltage, the voltage applied through the third wiring and the fourth wiring is maintained at a voltage less than the second voltage.
3. The semiconductor storage device according to claim 1 , wherein the voltage applied through the first wiring and the second wiring is increased to the second voltage if a current flowing through the first nonlinear element is less than a current threshold.
4. The semiconductor storage device according to claim 3 , wherein the current threshold is predetermined to be larger than the current flowing through the first nonlinear element at the threshold voltage.
5. The semiconductor storage device according to claim 2 , wherein
each of the first and second resistance change elements includes a magnetic resistance element.
6. The semiconductor storage device according to claim 2 , wherein
each of the first and second nonlinear elements contains a chalcogen.
7. The semiconductor storage device according to claim 2 , wherein
each of the first and second nonlinear elements includes a metal layer containing at least one of silver (Ag) and copper (Cu), or an insulating layer.
8. A semiconductor storage device, comprising:
a first wiring;
a first resistance change element connected to the first wiring;
a first nonlinear element connected to the first resistance change element;
a second wiring connected to the first nonlinear element; and
a peripheral circuit connected to the first wiring and the second wiring, wherein
in a read operation for the first resistance change element, the peripheral circuit is configured to:
increase a voltage applied through the first wiring and the second wiring until a current flowing through the first resistance change element is greater than a first current, where the voltage is determined according to a histogram of read threshold voltages of a plurality of memory cells in the semiconductor storage device.
9. The semiconductor storage device according to claim 8 , wherein
the first resistance change element includes a magnetic resistance element.
10. The semiconductor storage device according to claim 8 , wherein
the first nonlinear element contains a chalcogen.
11. The semiconductor storage device according to claim 8 , wherein
the first nonlinear element includes a metal layer containing at least one of silver (Ag) and copper (Cu), and an insulating layer.
12. The semiconductor storage device according to claim 8 , wherein the peripheral circuit is further configured to:
output a first signal if the current flowing through the first resistance change element is greater than the first current and less than a second current, and output a second signal if the current flowing through the first resistance change element is greater than the first current and the second current.
13. A method comprising:
selecting a first voltage according to a histogram of read threshold voltages of a plurality of memory cells, each memory cell including a resistance change element and nonlinear element coupled to each other;
applying the first voltage on one of the plurality of memory cells;
comparing a current flowing through the memory cell with a first current threshold;
selectively increasing the first voltage to an amplitude determined according to the histogram until the current reaches the first current threshold; and
outputting a state of data stored in the memory cell based on the comparison of the current with a second current threshold.