Semiconductor device including memory cell arrays and method of manufacturing the same

1. A semiconductor device comprising:

a first chip including:

a first substrate including a first region and a second region on a surface of the first substrate;

a first control circuit provided on the first substrate in the first region; and

a second control circuit provided on the first substrate in the second region;

a second chip including:

a first memory cell array provided above the first control circuit in the first region and electrically connected to the first control circuit; and

a second memory cell array provided above the second control circuit in the second region and electrically connected to the second control circuit;

a first metal pad provided on a boundary surface between the first chip and the second chip and electrically connecting the first control circuit and the first memory cell array;

a second metal pad provided on the boundary surface between the first chip and the second chip and electrically connecting the second control circuit and the second memory cell array;

a first pad provided above the first memory cell array in the first region and electrically connected to the first control circuit;

a second pad provided above the second memory cell array in the second region and electrically connected to the second control circuit; and

a connection line provided above the first memory cell array and the second memory cell array and electrically connecting the first pad to the second pad.

2. The device of claim 1 , wherein the first pad, the second pad and the connection line are continuous with one another in a metal layer.

3. The device of claim 1 , further comprising a second substrate provided above the first memory cell array and the second memory cell array.

4. The device of claim 3 , wherein the first pad, the second pad and the connection line are provided above the second substrate.

5. The device of claim 4 , wherein the first and second pads are electrically connected to the first and second control circuits, respectively, via plugs provided in the second substrate.

6. The device of claim 1 , wherein one of the first and second pads is a bonding pad, and the other of the first and second pads is not a bonding pad.

7. The device of claim 6 , further comprising an insulator having an opening only on the bonding pad out of the first and second pads.

8. A semiconductor device comprising:

a first substrate;

a first control circuit provided above the first substrate;

a first memory cell array provided above the first substrate and electrically connected to the first control circuit;

a first pad provided above the first memory cell array and electrically connected to the first control circuit; and

a connection line provided above the first memory cell array, including one end that is electrically connected to the first pad, and including the other end that extends in a first direction perpendicular to a surface of the first substrate to a position where the other end overlaps with an end face of the first substrate such that the other end is electrically open.

9. The device of claim 8 , wherein the first pad and the connection line are continuous with each other in a metal layer.

10. The device of claim 8 , further comprising a second substrate provided above the first memory cell array.

11. The device of claim 10 , wherein the first pad and the connection line are provided above the second substrate.

12. The device of claim 11 , wherein the first pad is electrically connected to the first control circuit via a plug that is provided in the second substrate.

13. The device of claim 8 , wherein the first pad is a bonding pad.