Semiconductor memory device

1. A semiconductor memory device comprising:

a bit line electrically connected to a memory cell;

a first node electrically connected to the bit line;

a first driver configured to increase a voltage of the first node to a first voltage;

a first buffer circuit configured to store data based on the voltage of the first node;

a bus electrically connected to the first buffer circuit;

a first transistor electrically connected between the first node and the bus;

a second transistor electrically connected between the first buffer circuit and the bus; and

a second buffer circuit electrically connected to the bus,

wherein:

the first buffer circuit includes a third transistor electrically connected to the second transistor;

the first buffer circuit is electrically connected to an input terminal of the first driver;

an output terminal of the first driver is electrically connected to a second node between the bit line and the first node;

the first driver changes a voltage of the bus based on the data stored in the first buffer circuit; and

the voltage of the bus is decreased or increased by setting the first transistor and the second transistor to a conducting state.

2. The semiconductor memory device according to claim 1 , further comprising a fourth transistor electrically connected between the bit line and the first node,

wherein the fourth transistor is set to a non-conducting state while the voltage of the bus is decreased or increased.

3. The semiconductor memory device according to claim 1 , wherein:

the first driver includes a first n-channel MOS field-effect transistor and a first p-channel MOS field-effect transistor;

the first n-channel MOS field-effect transistor is set to a conducting state while the voltage of the bus is decreased; and

the first p-channel MOS field-effect transistor is set to a conducting state while the voltage of the bus is increased.

4. The semiconductor memory device according to claim 1 , wherein:

the first buffer circuit includes a latch circuit including a first inverter and a second inverter, the first inverter and the second inverter each including an input terminal and an output terminal, the input terminal of the first inverter and the output terminal of the second inverter being electrically connected to each other, the input terminal of the second inverter and the output terminal of the first inverter being electrically connected to each other;

the output terminal of the first inverter is electrically connected to the input terminal of the first driver; and

the output terminal of the second inverter is electrically connected to the second transistor.

5. The semiconductor memory device according to claim 4 , wherein:

the second inverter includes a second n-channel MOS field-effect transistor and a second p-channel MOS field-effect transistor; and

while the voltage of the bus is decreased, the second n-channel MOS field-effect transistor is set to a conducting state, and the second p-channel MOS field-effect transistor is set to a non-conducting state.

6. The semiconductor memory device according to claim 1 , wherein the first driver increases the bit line to the first voltage before decreasing or increasing the voltage of the bus.

7. The semiconductor memory device according to claim 1 , wherein the first transistor is set to a conducting state before the second transistor is set to a conducting state.

8. The semiconductor memory device according to claim 1 , further comprising a fifth transistor including a first terminal electrically connected to the bus and a second terminal supplied with the first voltage; and

a sixth transistor electrically connected between the bus and the second buffer circuit.

9. A semiconductor memory device comprising:

a bit line electrically connected to a memory cell;

a first transistor electrically connected to the bit line;

a second transistor electrically connected to the first transistor via a first node;

a first driver electrically connected to the first node and configured to apply a first voltage to the bit line;

a third transistor electrically connected to the second transistor via a second node;

a bus electrically connected to the third transistor;

a fourth transistor including a gate electrically connected to the second node;

a first storage circuit including a first terminal and a second terminal, the first terminal being electrically connected to the fourth transistor;

a fifth transistor electrically connected between the first terminal of the first storage circuit and the bus; and

a second storage circuit electrically connected to the bus, wherein:

the first storage circuit includes a sixth transistor electrically connected to the fifth transistor;

the second terminal of the first storage circuit is electrically connected to an input terminal of the first driver;

an output terminal of the first driver is electrically connected to the first node between the first transistor and the second transistor;

the first driver decreases or increases a voltage of the bus based on a voltage of the second terminal of the first storage circuit; and

the voltage of the bus is decreased or increased by setting the third transistor and the fifth transistor to a conducting state.

10. The semiconductor memory device according to claim 9 , wherein the second transistor is set to a non-conducting state while the voltage of the bus is decreased or increased.

11. The semiconductor memory device according to claim 9 , wherein:

the first driver includes a first n-channel MOS field-effect transistor and a first p-channel MOS field-effect transistor;

the first n-channel MOS field-effect transistor is set to a conducting state while the voltage of the bus is decreased; and

the first p-channel MOS field-effect transistor is set to a conducting state while the voltage of the bus is increased.

12. The semiconductor memory device according to claim 9 , wherein:

the first storage circuit includes a latch circuit including a first inverter and a second inverter, the first inverter and the second inverter each including an input terminal and an output terminal, the input terminal of the first inverter and the output terminal of the second inverter being electrically connected to each other, the input terminal of the second inverter and the output terminal of the first inverter being electrically connected to each other;

the output terminal of the first inverter is electrically connected to the input terminal of the first driver; and

the output terminal of the second inverter is electrically connected to the fifth transistor.

13. The semiconductor memory device according to claim 12 , wherein:

the second inverter includes a second n-channel MOS field-effect transistor and a second p-channel MOS field-effect transistor; and

while the voltage of the bus is decreased, the second n-channel MOS field-effect transistor is set to a conducting state, and the second p-channel MOS field-effect transistor is set to a non-conducting state.

14. The semiconductor memory device according to claim 9 , wherein the first driver increases the bit line to the first voltage before decreasing or increasing the voltage of the bus.

15. The semiconductor memory device according to claim 9 , wherein the third transistor is set to a conducting state before the fifth transistor is set to a conducting state.

16. The semiconductor memory device according to claim 9 , further comprising:

a seventh transistor including a first terminal electrically connected to the bus and a second terminal supplied with the first voltage; and

an eighth transistor electrically connected between the bus and the second storage circuit.