Semiconductor memory device to hold 5-bits of data per memory cell
According to one embodiment, a semiconductor memory device includes: a memory cell configured to hold 5-bit data; a word line coupled to the memory cell; and a row decoder configured to apply first to 31st voltages to the word line. A first bit of the 5-bit data is established by reading operations using first to sixth voltages. A second bit of the 5-bit data is established by reading operations using seventh to twelfth voltages. A third bit of the 5-bit data is established by reading operations using thirteenth to eighteenth voltages. A fourth bit of the 5-bit data is established by reading operations using nineteenth to 25th voltages. A fifth bit of the 5-bit data is established by reading operations using 26th to 31st voltages.
1. A semiconductor memory device comprising
a memory cell configured to hold 5-bit data according to a threshold;
a word line coupled to the memory cell; and
a row decoder configured to apply first to 31st voltages to the word line,
wherein a first bit of the 5-bit data is established by reading operations using first to sixth voltages,
a second bit of the 5-bit data is established by reading operations using seventh to twelfth voltages, the second bit being different from the first bit,
a third bit of the 5-bit data is established by reading operations using thirteenth to eighteenth voltages, the third bit being different from the first and second bits,
a fourth bit of the 5-bit data is established by reading operations using nineteenth to 25th voltages, the fourth bit being different from the first to third bits, and
a fifth bit of the 5-bit data is established by reading operations using 26th to 31st voltages, the fifth bit being different from the first to fourth bits, and
wherein the first to 31st voltages are different voltages,
the row decoder applies the first to 31st voltages to the word line in ascending order, and
a reading operation using a 21st-applied voltage first establishes one of the first to fifth bits.
2. The device according to claim 1 , wherein a lowest voltage and a highest voltage among the first to 31st voltages are used to establish different bits.
3. The device according to claim 1 , wherein the first voltage is a lowest voltage and the 31st voltage is a highest voltage among the first to 31st voltages.
4. The device according to claim 1 , further comprising a holding circuit configured to hold the first to fifth bits read from the memory cell,
wherein the holding circuit outputs the first to fifth bits in an order that the bits are established.
5. A semiconductor memory device comprising:
a memory cell configured to hold 5-bit data according to a threshold;
a word line coupled to the memory cell; and
a row decoder configured to apply first to 31st voltages to the word line,
wherein a first bit of the 5-bit data is established by reading operations using first to fifth voltages,
a second bit of the 5-bit data is established by reading operations using sixth to twelfth voltages, the second bit being different from the first bit,
a third bit of the 5-bit data is established by reading operations using thirteenth to nineteenth voltages, the third bit being different from the first and second bits,
a fourth bit of the 5-bit data is established by reading operations using 20th to 26th voltages, the fourth bit being different from the first to third bits, and
a fifth bit of the 5-bit data is established by reading operations using 27th to 31st voltages, the fifth bit being different from the first to fourth bits, and
wherein the first to 31st voltages are different voltages,
the row decoder applies the first to 31st voltages to the word line in ascending order, and
a reading operation using a 20th-applied voltage first established one of the first to fifth bits.
6. The device according to claim 5 , wherein a lowest voltage and a highest voltage among the first to 31st voltages are used to establish different bits.
7. The device according to claim 5 , wherein the first voltage is a lowest voltage and the 31st voltage is a highest voltage among the first to 31st voltages.
8. The device according to claim 5 , further comprising a holding circuit configured to hold the first to fifth bits read from the memory cell,
wherein the holding circuit outputs the first to fifth bits in an order that the bits are established.
9. A semiconductor memory device comprising:
a memory cell configured to hold 5-bit data according to a threshold;
a word line coupled to the memory cell; and
a row decoder configured to apply first to 31st voltages to the word line,
wherein a first bit of the 5-bit data is established by reading operations using first to sixth voltages,
a second bit of the 5-bit data is established by reading operations using seventh to thirteenth voltages, the second bit being different from the first bit,
a third bit of the 5-bit data is established by reading operations using fourteenth to 20th voltages, the third bit being different from the first and second bits,
a fourth bit of the 5-bit data is established by reading operations using 21st to 27th voltages, the fourth bit being different from the first to third bits, and
a fifth bit of the 5-bit data is established by reading operations using 28th to 31st voltages, the fifth bit being different from the first to fourth bits, and
wherein the first to 31st voltages are different voltages;
the 28th voltage is a lowest voltage and the 31st voltage is a highest voltage among the first to 31st voltages.
10. The device according to claim 9 , wherein a lowest voltage and a highest voltage among the first to 31st voltages are used to establish an identical bit.
11. The device according to claim 9 , wherein the row decoder applies the first to 31st voltages to the word line in ascending order, and
a reading operation using a 22nd-applied voltage first establishes one of the first to fifth bits.
12. The device according to claim 11 , further comprising a holding circuit configured to hold the first to fifth bits read from the memory cell,
wherein the holding circuit outputs the first to fifth bits in an order that the bits are established.
13. A semiconductor memory device comprising:
a memory cell configured to hold 5-bit data according to a threshold;
a word line coupled to the memory cell; and
a row decoder configured to apply first to 31st voltages to the word line,
wherein a first bit of the 5-bit data is established by reading operations using first to sixth voltages,
a second bit of the 5-bit data is established by reading operations using seventh to thirteenth voltages, the second bit being different from the first bit,
a third bit of the 5-bit data is established by reading operations using fourteenth to 20th voltages, the third bit being different from the first and second bits,
a fourth bit of the 5-bit data is established by reading operations using 21st to 27th voltages, the fourth bit being different from the first to third bits, and
a fifth bit of the 5-bit data is established by reading operations using 28th to 31st voltages, the fifth bit being different from the first to fourth bits, and
wherein the first to 31st voltages are different voltages,
the row decoder applies the first to 31st voltages to the word line in ascending order, and
a reading operation using a 22nd-applied voltage first establishes one of the first to fifth bits.
14. The device according to claim 13 , further comprising a holding circuit configured to hold the first to fifth bits read from the memory cell,
wherein the holding circuit outputs the first to fifth bits in an order that the bits are established.
15. A semiconductor memory device comprising:
a memory cell configured to hold 5-bit data according to a threshold;
a word line coupled to the memory cell; and
a row decoder configured to apply first to 31st voltages to the word line,
wherein a first bit of the 5-bit data is established by reading operations using first to sixth voltages,
a second bit of the 5-bit data is established by reading operations using seventh to thirteenth voltages, the second bit being different from the first bit,
a third bit of the 5-bit data is established by reading operations using fourteenth to 20th voltages, the third bit being different from the first and second bits,
a fourth bit of the 5-bit data is established by reading operations using 21st to 27th voltages, the fourth bit being different from the first to third bits, and
a fifth bit of the 5-bit data is established by reading operations using 28th to 31st voltages, the fifth bit being different from the first to fourth bits, and
wherein the first to 31st voltages are different voltages,
the row decoder applies the first to 31st voltages to the word line in ascending order, and
a reading operation using a nineteenth-applied voltage first establishes one of the first to fifth bits.
16. The device according to claim 15 , further comprising a holding circuit configured to hold the first to fifth bits read from the memory cell,
wherein the holding circuit outputs the first to fifth bits in an order that the bits are established.
17. The device according to claim 9 , wherein a lowest voltage and a highest voltage among the first to 31st voltages are used to establish different bits.
18. The device according to claim 9 , wherein the first voltage is a lowest voltage and the 31st voltage is a highest voltage among the first to 31st voltages.