IP Library Granted Patent US 11,074,015
Granted Patent B2
US 11,074,015 · App. 16/564,396 · Granted Jul 27, 2021

Memory system and method for controlling nonvolatile memory by a host

Inventor: Shinichi Kanno (Ota, JP)
Assignee: TOSHIBA MEMORY CORPORATION
G06F3/0659G06F3/0604G06F3/064G06F3/0679
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Quick Facts
Patent No.
US 11,074,015
App. No.
16/564,396
Granted
Jul 27, 2021
Kind
B2
Abstract

According to one embodiment, a memory system receives from a host read commands each designating both of a block address of a read target block and a read target storage location in the read target block, and executes a data read operation in accordance with each of the received read commands. In response to receiving from the host a first command to transition a first block to which data is already written to a reusable state of being reusable as a new write destination block, the memory system determine whether an incomplete read command designating a block address of the first block exists or not. In a case where the incomplete read command exists, the memory system executes the first command after execution of the incomplete read command is completed.

Claims (54)

1. A memory system connectable to a host, the memory system comprising:

a nonvolatile memory including a plurality of blocks; and

a controller electrically connected to the nonvolatile memory and configured to receive from the host read commands each designating both of a block address of a read target block of the blocks and a read target storage location in the read target block, and to execute a data read operation in accordance with each of the received read commands, wherein

the controller is configured to:

manage a counter value indicative of the number of read commands already received from the host and incomplete, for each block to which data is already written;

every time a read command is received from the host, increment a counter value corresponding to a block designated by a block address in the received read command by 1;

every time execution of the received read command is completed, decrement a counter value corresponding to a block designated by a block address in the complete read command by 1;

in response to receiving from the host a first command to transition a first block to which data is already written to a reusable state of being reusable as a new write destination block, determine whether an incomplete read command already received from the host and designating a block address of the first block exists or not, in accordance with whether a counter value corresponding to the first block is zero or not; and

in a case where the incomplete read command designating the block address of the first block exists, execute the first command after execution of the incomplete read command designating the block address of the first block is completed.

2. The memory system of claim 1 , wherein

the controller is configured, when a new read command designating the block address of the first block is received from the host after the first block is transitioned to the reusable state of being reusable as the new write destination block, to return a response indicative of failure of the received new read command to the host without executing the received new read command.

3. The memory system of claim 1 , wherein

the controller is configured, when receiving from the host a write command designating a first identifier of a plurality of identifiers for accessing a plurality of regions each being a subset of the plurality of blocks, to allocate one of blocks of a common free block group shared by the plurality of regions as a write destination block for a region corresponding to the first identifier and to write data associated with the write command to the write destination block, and

the first command is a command to return one of blocks allocated to one of the plural regions as the write destination block to the common free block group to set the block to be reusable as a new write destination block for any region, or a command to execute an erase operation for one of the plurality of blocks.

4. The memory system of claim 1 , wherein

the controller is configured, when receiving from the host the first command to transition the first block to the reusable state, to determine whether the incomplete read command already received from the host and designating the block address of the first block exists or not, by referring to a command queue in the controller where each of the incomplete commands is stored.

5. The memory system of claim 1 , wherein

the controller is configured to:

when receiving from the host the first command to transition the first block to the reusable state, further determine whether an incomplete copy command already received from the host and designating the block address of the first block as a block address of a copy source block exists or not; and

execute the first command after execution of both of the incomplete read command designating the block address of the first block and the incomplete copy command designating the block address of the first block as the block address of the copy source block is completed.

6. A memory system connectable to a host, the memory system comprising:

a nonvolatile memory including a plurality of blocks; and

a controller electrically connected to the nonvolatile memory and configured to receive from the host read commands each designating both of a block address of a read target block of the plurality of blocks and a read target storage location in the read target block, and to execute a data read operation in accordance with each of the received read commands, wherein

the controller is configured to:

manage a counter value indicative of the number of read commands already received from the host and incomplete, for each block to which data is already written;

every time a read command is received from the host, increment a counter value corresponding to a block designated by a block address in the received read command by 1;

every time execution of the received read command is completed, decrement a counter value corresponding to a block designated by a block address in the complete read command by 1;

in response to receiving from the host a first command to transition a first block to which data is already written to a reusable state of being reusable as a new write destination block, determine whether an incomplete read command already received from the host and designating a block address of the first block exists or not, in accordance with whether a counter value corresponding to the first block is zero or not;

in a case where the incomplete read command designating the block address of the first block does not exist, execute the first command; and

in a case where the incomplete read command designating the block address of the first block exists, return a response indicative of failure of the first command to the host without executing the first command.

7. The memory system of claim 6 , wherein

the controller is configured, when a new read command designating the block address of the first block is received from the host after the first block is transitioned to the reusable state of being reusable as the new write destination block, to return a response indicative of failure of the received new read command to the host without executing the received new read command.

8. The memory system of claim 6 , wherein

the controller is configured, when receiving from the host a write command designating a first identifier of a plurality of identifiers for accessing a plurality of regions each being a subset of the plurality of blocks, to allocate one of blocks of a common free block group shared by the plurality of regions as a write destination block for a region corresponding to the first identifier, and to write data associated with the write command to the write destination block, and

the first command is a command to return one of blocks allocated to one of the plurality of regions as the write destination block to the common free block group to set the block to be reusable as a new write destination block for any optional region, or a command to execute an erase operation for one of the plurality of blocks.

9. The memory system of claim 6 , wherein

the controller is configured, when receiving from the host the first command to transition the first block to the reusable state, to determine whether the incomplete read command already received from the host and designating the block address of the first block exists or not, by referring to a command queue in the controller where each of the incomplete commands is stored.

10. The memory system of claim 6 , wherein

the controller is configured to:

when receiving from the host the first command to transition the first block to the reusable state, further determine whether an incomplete copy command already received from the host and designating the block address of the first block as a block address of a copy source block exists or not; and

in a case where the incomplete read command designating the block address of the first block or the incomplete copy command designating the block address of the first block as the block address of the copy source block exists, return a response indicative of failure of the first command to the host without executing the first command.

11. A method of controlling a nonvolatile memory including a plurality of blocks, the method comprising:

receiving from a host each read commands each designating both of a block address of a read target block of the plurality of blocks and a read target storage location in the read target block;

executing a data read operation in accordance with each of the received read commands;

managing a counter value indicative of the number of read commands already received from the host and incomplete, for each block to which data is already written;

every time a read command is received from the host, incrementing a counter value corresponding to a block designated by a block address in the received read command by 1;

every time execution of the received read command is completed, decrementing a counter value corresponding to a block designated by a block address in the complete read command by 1;

in response to receiving from the host a first command to transition a first block to which data is already written to a reusable state of being reusable as a new write destination block, determining whether an incomplete read command already received from the host and designating a block address of the first block exists or not, in accordance with whether a counter value corresponding to the first block is zero or not; and

in a case where the incomplete read command designating the block address of the first block exists, executing the first command after execution of the incomplete read command designating the block address of the first block is completed.

12. The method of claim 11 , further comprising:

when a new read command designating the block address of the first block is received from the host after the first block is transitioned to the reusable state of being usable as the new write destination block, returning a response indicative of failure of the received new read command to the host without executing the received new read command.

13. The method of claim 11 , further comprising:

when receiving from the host a write command designating a first identifier of a plurality of identifiers for accessing a plurality of regions each being a subset of the plurality of blocks, allocating one of blocks of a common free block group shared by the plurality of regions as a write destination block for a region corresponding to the first identifier, and writing data associated with the write command to the write destination block,

wherein the first command is a command to return one of blocks allocated to one of the plurality of regions as the write destination block to the common free block group to set the block to be reusable as a new write destination block for any region, or a command to execute an erase operation for one of the plurality of blocks.

Assignments (2)
CHANGE OF NAME AND ADDRESS Recorded Jan 31, 2022
From: TOSHIBA MEMORY CORPORATION
To: KIOXIA CORPORATION
Reel/Frame 058905/0582 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 19, 2019
From: KANNO, SHINICHI
To: TOSHIBA MEMORY CORPORATION
Reel/Frame 051052/0059 →