Nonvolatile semiconductor memory device
According to the present embodiment, a nonvolatile semiconductor memory device includes a memory string group including k stacked memory strings, each of the memory strings including a plurality of nonvolatile memory cells connected in series, a selection transistor group including k selection transistors, each of the k selection transistors corresponding to each of the k memory strings respectively, the selection transistor group divided into n selection transistor sub-groups, each of the n selection transistor sub-groups including k/n selection transistors, n bit lines arranged in parallel to each of the k memory strings, and n bit line contacts arranged perpendicularly, each of the n bit line contacts connected to each of the n bit lines, respectively, each of the n bit line contacts connected to the k/n selection transistors belonging to the each of the n selection transistor sub-group respectively.
1. A nonvolatile semiconductor memory device comprising:
a memory string group including k stacked memory strings stacked in a stacking direction, each of the memory strings stacked in a different layer perpendicular to the stacking direction and including a plurality of nonvolatile memory cells connected in series, k being an integer of 2 or more;
a selection transistor group including k selection transistors, each of the k selection transistors corresponding to each of the k memory strings respectively, the selection transistor group divided into n selection transistor sub-groups, each of the n selection transistor sub-groups including k/n selection transistors, n being an integer of 2 or more;
n bit lines arranged in parallel to each of the k memory strings; and
n bit line contacts arranged perpendicularly, each of the n bit line contacts connected to each of the n bit lines respectively, each of the n bit line contacts connected to the k/n selection transistors belonging to the each of the n selection transistor sub-group respectively.
2. The nonvolatile semiconductor memory device according to claim 1 , wherein the k/n selection transistors belonging to the n selection transistor sub-group are stacked in the periphery of the corresponding n bit line contacts.
3. The nonvolatile semiconductor memory device according to claim 1 , wherein each of the k memory string forms a memory string pair on two columns, and a bit line is arranged at a pitch of ¼ of the pitch of the memory string pair is arranged, and n equals 4.
4. The nonvolatile semiconductor memory device according to claim 2 , wherein each of the n bit line contacts is formed with an insulation layer in a periphery of a part not connected with corresponding k/n selection transistors.
5. The nonvolatile semiconductor memory device according to claim 1 further comprising:
a row decoder for selecting a plurality of selection transistors at the same time for each of the n selection transistor sub-groups.
6. The nonvolatile semiconductor memory device according to claim 1 , wherein the memory string group connected with the selection transistor group forms one block.
7. The nonvolatile semiconductor memory device according to claim 6 , wherein a memory cell of a memory string belonging to the block is deleted for each block.
8. The nonvolatile semiconductor memory device according to claim 2 , wherein each of the k memory string forms a memory string pair on two columns, and a bit line is arranged at a pitch of ¼ of the pitch of the memory string pair is arranged, and n equals 4.
9. The nonvolatile semiconductor memory device according to claim 2 further comprising:
a row decoder for selecting a plurality of selection transistors at the same time for each of the n selection transistor sub-groups.
10. The nonvolatile semiconductor memory device according to claim 2 , wherein the memory string group connected with the selection transistor group forms one block.
11. The nonvolatile semiconductor memory device according to claim 10 , wherein a memory cell of a memory string belonging to the block is deleted for each block.
12. The nonvolatile semiconductor memory device according to claim 3 further comprising:
a row decoder for selecting a plurality of selection transistors at the same time for each of the n selection transistor sub-groups.
13. The nonvolatile semiconductor memory device according to claim 3 , wherein the memory string group connected with the selection transistor group forms one block.
14. The nonvolatile semiconductor memory device according to claim 13 , wherein a memory cell of a memory string belonging to the block is deleted for each block.
15. The nonvolatile semiconductor memory device according to claim 4 further comprising:
a row decoder for selecting a plurality of selection transistors at the same time for each of the n selection transistor sub-groups.
16. The nonvolatile semiconductor memory device according to claim 4 , wherein the memory string group connected with the selection transistor group forms one block.
17. The nonvolatile semiconductor memory device according to claim 16 , wherein a memory cell of a memory string belonging to the block is deleted for each block.
18. The nonvolatile semiconductor memory device according to claim 5 , wherein the memory string group connected with the selection transistor group forms one block.
19. The nonvolatile semiconductor memory device according to claim 18 , wherein a memory cell of a memory string belonging to the block is deleted for each block.