Large data read techniques
Devices and techniques are disclosed herein for more efficiently exchanging large amounts of data between a host and a storage system. In an example, a read command can optionally include a read-type indicator. The read-type indicator can allow for exchange of a large amount of data between the host and the storage system using a single read command.
1. A NAND memory device, comprising:
a controller configured to:
send a portion of a logical-to-physical (L2P) mapping table to a host device, the L2P mapping table including a mapping between a first logical address and a first physical address;
receive a read command from a host over a host interface, the read command including the first physical address;
operate the NAND memory device in a first mode to perform a read operation of a first number of bytes of data at the first physical address in response to a first configuration of the read command;
operate the NAND memory device in a second mode to perform a read operation of a second number of bytes of data at the first physical address and a plurality of second physical addresses, the second number greater than the first number in response to a second configuration of the read command and in response to receiving a parameter list message with the plurality of second physical addresses; and
wherein the second configuration of the read command includes a first one or more bits establishing a size of the second number.
2. The NAND memory device of claim 1 , wherein the second configuration of the read command includes a second one or more bits establishing a parameter list length.
3. The NAND memory device of claim 1 , wherein each of the second physical addresses address the first number of bytes of data of the second number of bytes of data.
4. The NAND memory device of claim 1 , wherein the first physical address addresses the first number of bytes of data.
5. The NAND memory device of claim 1 , wherein a state of a bit of the read command determines when the read command is in the first configuration or the second configuration.
6. The NAND memory device of claim 1 , including flash memory coupled to the controller, the flash memory including the first number of bytes of data or the second number of bytes of data.
7. A method comprising:
at a controller of a NAND memory device:
sending a portion of a to (L2P) mapping table to a host device, the L2P mapping table including a mapping between a first logical address and a first physical address and a second mapping between a second logical address and a second physical address;
receiving a first read command from a host over a host interface, the first read command including the first physical address;
responsive to the receiving the first read command, operating the NAND memory device in a first mode to perform a read operation of a first number of bytes of data at the first physical address in response to a first configuration of the read command;
receiving a second read command from the host over the host interface, the second read command including the second physical address;
responsive to the second read command operating the NAND memory device in a second mode to perform a read operation of a second number of bytes of data at the second physical address and a plurality of third physical addresses, the second number greater than the first number in response to a second configuration of the second read command and in response to receiving a parameter list message with the plurality of third physical addresses; and
wherein the second configuration of the read command includes a first one or more bits establishing a site of the second number.
8. The method of claim 7 , wherein the second configuration of the second read command includes a second one or more bits establishing a parameter list length.
9. The method of claim 7 , wherein each of the third physical addresses address a first number of bytes of data of the second number of bytes of data.
10. The method of claim 7 , wherein the first physical address addresses the first number of bytes of data.
11. The method of claim 7 , wherein a state of a bit of a read command received at the NAND memory device determines when the read command is in the first configuration or the second configuration.
12. A non-transitory machine-readable medium, comprising instructions, which when executed by a processor of a flash memory device, cause the processor to perform operations comprising:
at a controller of a NAND memory device:
sending a portion of a logical-to-physical (L2P) mapping table to a host device, the L2P mapping table including a mapping between a first logical address and a first physical address and a second mapping between a second logical address and a second physical address;
receiving a first read command from a host over a host interface, the first read command including the first physical address;
responsive to the receiving the first read command, operating the NAND memory device in a first mode to perform a read operation of a first number of bytes of data at the first physical address in response to a first configuration of the read command;
receiving a second read command from the host over the host interface, the second read command including the second physical address;
responsive to the second read command operating the NAND memory device in a second mode to perform a read operation of a second number of bytes of data at the second physical address and a plurality of third physical addresses, the second number greater than the first number in response to a second configuration of the second read command and in response to receiving a parameter list message with the plurality of third physical addresses; and
wherein the second configuration of the read command includes a first one or more bits establishing a size of the second number.
13. The non-transitory machine-readable medium of claim 12 , wherein the second configuration of the second read command includes a second one or more bits establishing a parameter list length.
14. The non-transitory machine-readable medium of claim 12 , wherein each of the third physical addresses address a first number of bytes of data of the second number of bytes of data.
15. The non-transitory machine-readable medium of claim 12 , wherein the first physical address addresses a first read location including the first number of bytes of data.
16. The non-transitory machine-readable medium of claim 12 , wherein a state of a bit of a read command received at the NAND memory device determines when the read command is in the first configuration or the second configuration.