Memory system
A memory system includes a memory device including first storage elements which store data, a temperature sensor which measures a temperature of the memory device, and a controller including a processor which acquires a current temperature from the temperature sensor as a first temperature, acquires a temperature when the data is written into the first storage element, from the memory device as a second temperature, determines whether a difference between the first temperature and the second temperature exceeds a predetermined temperature difference, and when the difference exceeds the predetermined temperature difference, instructs the memory device to rewrite the data written in the first storage element. The memory device includes a sequencer which determines a voltage for the rewrite, based on the difference and a voltage when the data is written into the first storage element.
1. A memory system comprising:
a memory device including a plurality of first storage elements configured to store data;
a temperature sensor configured to measure a temperature of the memory device; and
a controller, wherein
the controller includes a processor configured to:
acquire a current temperature from the temperature sensor as a first temperature;
acquire a temperature when the data is written into the first storage element, from the memory device as a second temperature;
determine whether a difference between the first temperature and the second temperature exceeds a predetermined temperature difference; and
when the difference exceeds the predetermined temperature difference, instruct the memory device to rewrite the data written in the first storage element, and
the memory device includes a sequencer configured to determine a voltage for the rewrite, based on the difference and a voltage when the data is written into the first storage element, and
when the rewrite of the data is performed, the second temperature is updated and an updated second temperature is rewritten into a second storage element.
2. The memory system according to claim 1 , wherein
the processor is configured to check, at regular intervals, whether the difference exceeds the predetermined temperature difference.
3. The memory system according to claim 1 , wherein
the sequencer is configured to, when an instruction to rewrite the data is received from the controller, rewrite the data in an idle time of the memory device.
4. The memory system according to claim 1 , wherein
the second storage element is included in the memory device and configured to, when a write of the data is performed, be written the temperature acquired from the temperature sensor as the second temperature.
5. The memory system according to claim 4 , wherein
the controller includes a buffer configured to store the second temperature acquired upon boot,
the sequencer is configured to transmit the second temperature rewritten in the second storage element when the rewrite of the data is performed, to the controller, and
the processor is configured to update storage contents of the buffer, in response to the transmission of the second temperature from the memory device.
6. The memory system according to claim 1 , wherein
the memory device includes a block including a plurality of pages each including a plurality of the first storage elements,
the memory device is configured to perform a write of substantial data to be stored in the page unit,
the page includes:
a data area for writing the substantial data; and
a redundant area for writing associated data associated with the substantial data,
the second temperature is a temperature associated with the temperature of the memory device at a time of writing data in the page unit, which is acquired by the temperature sensor, and
the sequencer is configured to write the second temperature into the first storage element of the redundant area.
7. The memory system according to claim 6 , wherein
the memory device further includes a high reliability area including a second storage element that reliability of data read with respect to a temperature change is higher than the first storage element of the data area, and
the sequencer is configured to write the second temperature written in the first storage element of the redundant area of the page into the high reliability area together with address information of the page.
8. The memory system according to claim 7 , wherein
the sequencer is configured to, when the rewrite of the data is performed, update the second temperature and rewrite an updated second temperature into the high reliability area.
9. The memory system according to claim 8 , wherein
the controller includes a buffer configured to store the second temperature acquired upon boot,
the sequencer is configured to transmit the second temperature rewritten in the high reliability area when the rewrite of the data is performed, to the controller, and
the processor is configured to update storage contents of the buffer, in response to the transmission of the second temperature from the memory device.
10. The memory system according to claim 9 , wherein
the memory device is configured to erase the substantial data in the block unit,
the processor is configured to instruct the memory device to erase the substantial data in an erasure-target block, and
the sequencer is configured to, when the erase of the substantial data is performed, erase the second temperature written in the high reliability area corresponding to the block from which the substantial data has been erased.
11. The memory system according to claim 10 , wherein
the processor is configured to update the storage contents of the buffer corresponding to the block of the memory device instructed to erase.
12. The memory system according to claim 1 , wherein
the memory device includes:
a block including pages each including the first storage elements for writing substantial data to be stored; and
a high reliability area including a second storage element that reliability of data read with respect to a temperature change is higher than the first storage element for writing the substantial data,
the memory device is configured to perform a write of the substantial data in the page unit,
the second temperature is a block-unit temperature associated with a minimum temperature and a maximum temperature of temperatures of the memory device at times of writing data to each page in the block acquired by the temperature sensor, and
the sequencer is configured to write the second temperature into the high reliability area.
13. The memory system according to claim 12 , wherein
the sequencer is configured to
when writing data in the page unit, check whether either the minimum temperature or the maximum temperature at the acquired second temperature is out of a temperature range indicated by the second temperature already written in the high reliability area with respect to the block including the page to which the data has been written; and
when either the minimum temperature or the maximum temperature at the second temperature is out of the temperature range, update the second temperature acquired out of the range and record an updated second temperature into the high reliability area.
14. The memory system according to claim 13 , wherein
the sequencer is configured to, when the rewrite of the data is performed, update the second temperature and rewrite an updated second temperature into the high reliability area.
15. The memory system according to claim 14 , wherein:
the controller includes a buffer configured to store the second temperature acquired upon boot,
the sequencer is configured to transmit the second temperature rewritten in the high reliability area when the rewrite of the data is performed, to the controller, and
the processor is configured to update storage contents of the buffer in response to the transmission of the second temperature from the memory device.
16. The memory system according to claim 15 , wherein
the memory device is configured to erase the substantial data in the block unit,
the processor is configured to instruct the memory device to erase the substantial data in an erasure-target block, and
the sequencer is configured to, when the erase of the substantial data is performed, erase the second temperature written in the high reliability area corresponding to the block from which the substantial data has been erased.
17. The memory system according to claim 16 , wherein
the processor is configured to update the storage contents of the buffer corresponding to the block of the memory device instructed to erase.