Memory device, operating method thereof, and operating method of memory system including the same

1. An operating method of a rnmemory device, comprising:

receiving a write command;

checking out whether a data strobe signal transferred from a memory controller toggles or maintains a uniform level after a time period equal to a write latency passes from a moment when the write command is received;

when the data strobe signal maintains the uniform level, detecting voltage levels of a plurality of data pads; and

writing a data pattern at is selected based on the voltage levels of the plurality of the data pads, from a plurality of data patterns,

wherein, when the data strobe signal maintains the uniform level, the voltage levels of the plurality of the data pads are fixed for at least two or more clock cycles after the time period passes from the moment when the write command is received.

2. An operating method of a memory device, comprising:

receiving a write command;

checking out whether a data strobe signal transferred from a memory controller toggles or maintains a uniform level after a time period equal to a write latency passes from a moment when the write command is receive;

when the data strobe signal maintains the uniform level, detecting voltage levels of a plurality of data pads and deciding to perform a re-write operation in response to the detecting; and

reading a data from a selected region, inverting the read data to produce an inverted read data, and re-writing the inverted read data in the selected region,

wherein, when the data strobe signal maintains the uniform level, the voltage levels of the plurality of the data pads are fixed for at least two or more clock cycles after the time period passes from the moment when the write command is received.

3. The operating method of claim 1 , further comprising:

when the data strobe signal toggles, writing data received through the plurality of the data pads in the memory device in synchronization with the data strobe signal.

4. The operating method of claim 1 , wherein, when the data strobe signal maintains the uniform level, the voltage levels of the plurality of the data pads are fixed for at least two or more clock cycles after the time period passes from the moment when the write command is received.

5. An operating method of a memory system, comprising:

transferring a write command from a memory controller to a memory device;

transferring a data strobe signal of a fixed level from the memory controller to the memory device after a time period equal to a write latency passes from a moment when the write command is transferred;

the memory controller fixing voltage levels of data lines at for at least two or more clock cycles after the time period passes from the moment when the write command is transferred; and

the memory device writing a data pattern that is selected based on the voltage levels of the plurality of data lines, from a plurality of data patterns.

6. An operating method of a memory system, comprising:

transferring a write command from a memory controller to a memory device;

transferring a data strobe signal of a fixed level from the memory controller to the memory device after a time period equal to a write latency passes from a moment whenthe write command is transferred;

the memory controller fixing voltage levels of data lines at for at least two or more clock cycles after the time period passes from the moment when the write command is transferred;

the memory device deciding to perform a re-write operation in response to the voltage levels of data lines; and

the memory device reading a data from a region that is selected in the memory device, inverting the read data to produce an inverted read data, and re-writing the inverted read data in the selected region.