Memory cell array having three-dimensional structure

1. A semiconductor memory comprising:

a first bit line;

a second bit line;

a source line;

a first memory cell electrically connected between the first bit line and the source line and including a first transistor and a first capacitor;

a second memory cell electrically connected between the second bit line and the source line and including a second transistor and a second capacitor;

a third transistor electrically connected to the source line; and

a sense amplifier circuit including:

a first node electrically connected to the first bit line and a second node electrically connected to the second bit line;

a first sense unit including a first input terminal electrically connected to the first node via a first transfer gate and a second input terminal electrically connected to the second node via a second transfer gate;

a second sense unit including a third input terminal electrically connected to the first node and a fourth input terminal electrically connected to the second node;

a first capacitor including a first terminal electrically connected to the first input terminal of the first sense unit and a second terminal electrically connected to the fourth input terminal of the second sense unit; and

a second capacitor including a third terminal electrically connected to the second input terminal of the first sense unit and a fourth terminal electrically connected to the third input terminal of the second sense unit.

2. The semiconductor memory according to claim 1 , wherein:

a read operation for the first memory cell includes reading of data from the first memory cell and writing of data to the first memory cell after the reading of data; and

a write voltage for the writing of data is applied to the source line.

3. The semiconductor memory according to claim 2 , wherein the source line is electrically connected to the second bit line during the writing of data to the first memory cell.

4. The semiconductor memory according to claim 1 ,

further comprising:

a fourth transistor including a fifth terminal electrically connected to the first bit line and a sixth terminal electrically connected to the source line; and

a fifth transistor including a seventh terminal electrically connected to the second bit line and an eighth terminal electrically connected to the source line.

5. The semiconductor memory according to claim 4 , wherein:

the fifth terminal is electrically connected to the first input terminal of the first sense unit via the first bit line; and

the seventh terminal is electrically connected to the second input terminal of the first sense unit via the second bit line.

6. The semiconductor memory according to claim 4 , wherein:

a read operation for the first memory cell includes reading of data from the first memory cell and writing of data to the first memory cell after the reading of data;

the fifth transistor is set in an on state when the reading of data and the writing of data; and

a write voltage for the writing of data is applied to the source line via the fifth transistor having the on state.

7. The semiconductor memory according to claim 1 , wherein if a first capacitance of one of the first and second input terminals of the first sense unit, a second capacitance of one of the third and fourth input terminals of the second sense unit and a third capacitance of the source line are represented as “CA,” “CB” and “Cx,” respectively, there is a following relationship among the first capacitance, the second capacitance and the third capacitance:

CB =( Cx×CA )/(2×( Cx+CA )).

8. The semiconductor memory according to claim 1 , further comprising:

a sixth transistor including a ninth terminal electrically connected to the source line and a tenth terminal electrically connected to a first interconnect.

9. The semiconductor memory according to claim 1 , wherein the first memory cell stores data of two or more bits.

10. A semiconductor memory comprising:

a first bit line provided above a semiconductor substrate in a first direction perpendicular to a first surface of the semiconductor substrate;

a second bit line provided above the first bit line in the first direction;

a source line provided between the first bit line and the second bit line;

a first memory cell including a first transistor provided between the first bit line and the source line and a first capacitor provided between the first transistor and the source line;

a second memory cell including a second transistor provided between the second bit line and the source line and a second capacitor provided between the second transistor and the source line;

a first word line provided between the first bit line and the source line and connected to a gate of the first transistor;

a second word line provided between the second bit line and the source line and connected to a gate of the second transistor;

a sense amplifier circuit provided on the semiconductor substrate; and

a third transistor provided between the semiconductor substrate and the source line,

wherein the sense amplifier circuit includes:

a first node electrically connected to the first bit line and a second node electrically connected to the second bit line,

a first sense unit including a first input terminal electrically connected to the first node via a first transfer gate and a second input terminal electrically connected to the second node via a second transfer gate;

a second sense unit including a third input terminal electrically connected to the first node and a fourth input terminal electrically connected to the second node;

a first capacitor including a first terminal electrically connected to the first input terminal of the first sense unit and a second terminal electrically connected to the fourth input terminal of the second sense unit; and

a second capacitor including a third terminal electrically connected to the second input terminal of the first sense unit and a fourth terminal electrically connected to the third input terminal of the second sense unit.

11. The semiconductor memory according to claim 10 , further comprising a first plug provided between the third transistor and the semiconductor substrate.

12. The semiconductor memory according to claim 10 , further comprising:

a fourth transistor provided between the first bit line and the source line; and

a fifth transistor provided between the second bit line and the source line.

13. The semiconductor memory according to claim 10 , further comprising:

an interconnect provided above the semiconductor substrate in the first direction; and

a sixth transistor provided between the interconnect and the source line.

14. The semiconductor memory according to claim 10 , wherein

the first and second bit lines and the source line extend to a second direction parallel to the first surface of the semiconductor substrate, and

the first and second word lines extend to a third direction parallel to the first surface of the semiconductor substrate and intersecting the first and second direction.

15. The semiconductor memory according to claim 10 ,

wherein if a first capacitance of one of the first and second input terminals of the first sense unit, a second capacitance of one of the third and fourth input terminals of the second sense unit and a third capacitance of the source line are represented as “CA,” “CB” and “Cx,” respectively, there is a following relationship among the first capacitance, the second capacitance and the third capacitance:

CB =( Cx×CA )/(2×( Cx+CA )).

16. The semiconductor memory according to claim 10 , wherein the first memory cell stores data of two or more bits.