IP Library › Granted Patent US 10,847,192

Granted Patent B2

US 10,847,192 · App. 16/568,662 · Granted Nov 24, 2020

Semiconductor memory device

Inventors: Marie Takada (Yokohama, JP); Masanobu Shirakawa (Chigasaki, JP); Takuya Futatsuyama (Yokohama, JP)

Assignee: Toshiba Memory Corporation

G11C5/063 G11C7/08 G11C16/08 G11C16/10 G11C16/24 G11C16/26 H01L23/5226 H01L27/1157 H01L27/11582

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Quick Facts

Patent No.: US 10,847,192
App. No.: 16/568,662
Granted: Nov 24, 2020
Kind: B2

External Links

USPTO Patent Center↗ Full Patent PDF↗

Abstract

According to one embodiment, a semiconductor memory device includes: a first memory cell; a second memory cell; a first word line; a second word line; and a first bit line. The first memory cell faces the second memory cell. When reading data from the first memory cell, the semiconductor memory device is configured to perform the first operation in which a first voltage is applied to the first word line and a second voltage higher than the first voltage is applied to the second word line, and perform the second operation in which a third voltage higher than the first voltage and a fourth voltage different from the third voltage are applied to the first word line and a fifth voltage lower than the second to the fourth voltage is applied to the second word line.

Claims (128)

1. A semiconductor memory device comprising:

a first memory cell;

a second memory cell;

a first word line coupled to the first memory cell;

a second word line coupled to the second memory cell; and

a first bit line capable of being electrically coupled to both the first memory cell and the second memory cell,

wherein the first memory cell faces the second memory cell with a first semiconductor layer interposed therebetween,

the semiconductor memory device is configured to perform a data read operation including a first operation and a second operation, and

when reading data from the first memory cell, the semiconductor memory device is configured to

perform the first operation in which a first voltage is applied to the first word line and a second voltage higher than the first voltage is applied to the second word line, and

perform, after the first operation, the second operation in which a third voltage higher than the first voltage and a fourth voltage different from the third voltage are applied to the first word line and a fifth voltage lower than the second to the fourth voltage is applied to the second word line, and

wherein the first voltage and the fifth voltage turn off a memory cell.

2. The device according to claim 1 , further comprising a first sense amplifier configured to determine data based on a voltage of the first bit line or a current in the first bit line in the data read operation,

wherein, when reading data from the first memory cell, the first sense amplifier is configured to

determine data in a period during the third voltage is applied to the first word line in the second operation, when the second memory cell turns on in the first operation, and

determine data in a period during the fourth voltage is applied to the first word line in the second operation, when the second memory cell turns off in the first operation.

3. The device according to claim 2 , further comprising:

a third memory cell;

a fourth memory cell coupled to the first word line;

a third word line coupled to the third memory cell;

a second bit line capable of being electrically coupled to both the third memory cell and the fourth memory cell;

a first transistor configured to couple the first memory cell with the first bit line;

a second transistor configured to couple the second memory cell with the first bit line;

a third transistor configured to couple the third memory cell with the second bit line; and

a fourth transistor configured to couple the fourth memory cell with the second bit line;

wherein the third memory cell faces the fourth memory cell with a second semiconductor layer interposed therebetween,

data stored in the first memory cell and the fourth memory cell is read in parallel,

when reading data from the first memory cell and the fourth memory cell, the semiconductor memory device is configured to

perform the first operation in which the second transistor is turned on and data is read from the second memory cell, and

perform the second operation in which the first transistor and the fourth transistor are turned on and data is read from the first memory cell and the fourth memory cell,

wherein the third transistor is kept off during a period of reading the data from the first memory cell and the fourth memory cell.

4. The device according to claim 3 , wherein data is written into the first memory cell and the fourth memory cell in parallel,

data is written into the second memory cell after the data is written into the first memory cell and the fourth memory cell, and

data is written into the third memory cell before the data is written into the first memory cell and the fourth memory cell.

5. The device according to claim 1 , further comprising:

a third memory cell;

a fourth memory cell coupled to the first word line;

a third word line coupled to the third memory cell; and

a second bit line capable of being electrically coupled to both the third memory cell and the fourth memory cell,

wherein the third memory cell faces the fourth memory cell with a second semiconductor layer interposed therebetween,

the data read operation further includes a third operation before the second operation,

data stored in the first memory cell and the fourth memory cell is read in parallel, and

when reading data from the first memory cell and the fourth memory cell, the semiconductor memory device is configured to

perform the third operation in which a sixth voltage is applied to the first word line and a seventh voltage higher than the sixth voltage is applied to the third word line, and

perform the second operation in which an eighth voltage lower than the second to the fourth, and the seventh voltage is applied to the third word line, and

wherein the sixth voltage and the eighth voltage turn off a memory cell.

6. The device according to claim 5 , further comprising a second sense amplifier configured to determine data based on a voltage of the second bit line or a current in the second bit line in the data read operation,

wherein, when reading data from the fourth memory cell, the second sense amplifier is configured to

determine data in a period during the third voltage is applied to the first word line in the second operation, when the third memory cell is turned on in the third operation, and

determine data in a period during the fourth voltage is applied to the first word line in the second operation, when the third memory cell is turned off in the third operation.

7. The device according to claim 6 , wherein data is written into the first memory cell and the fourth memory cell in parallel,

data is written into the second memory cell and the third memory cell after the data is written into the first memory cell and the fourth memory cell.

8. The device according to claim 1 , further comprising:

a third memory cell;

a fourth memory cell;

a third word line coupled to the third memory cell; and

a fourth word line coupled to the fourth memory cell,

wherein the third memory cell faces the fourth memory cell with a second semiconductor layer interposed therebetween,

the first bit line is capable of being electrically coupled to both the third memory cell and the fourth memory cell,

the data read operation further includes a third operation before the second operation, and

when reading data from the first memory cell, the semiconductor memory device is configured to

perform the third operation in which a sixth voltage is applied to the third word line, a seventh voltage higher than the sixth voltage is applied to the first word line, an eighth voltage is applied to the second word line, and a ninth voltage is applied to the fourth word line, and

perform the second operation in which a tenth voltage different from the third voltage and the fourth voltage is applied to the first word line, and an eleventh voltage different from the third to the fifth voltage is further applied to the first word line, and

wherein the seventh voltage turns on a memory cell, and

the eighth voltage and the ninth voltage turn off a memory cell.

9. The device according to claim 8 , wherein the third memory cell is electrically coupled between the first memory cell and the first bit line, and

the fourth memory cell is electrically coupled between the second memory cell and the first bit line.

10. The device according to claim 8 , further comprising a first sense amplifier configured to determine data based on a voltage of the first bit line or a current in the first bit line in the data read operation,

wherein, when reading data from the first memory cell, the first sense amplifier is configured to:

determine data in a period during the third voltage is applied to the first word line in the second operation, when the second memory cell turns on in the first operation and the third memory cell turns on in the third operation, and

determine data in a period during the eleventh voltage is applied to the first word line in the second operation, when the second memory cell turns off in the first operation and the third memory cell turns off in the third operation.

11. The device according to claim 10 , wherein the eleventh voltage is higher than the third voltage.

12. The device according to claim 10 , wherein the first sense amplifier is configured to:

determine data in a period during the fourth voltage is applied to the first word line in the second operation, when the second memory cell turns on in the first operation and the third memory cell turns off in the third operation, and

determine data in a period during the tenth voltage is applied to the first word line in the second operation, when the second memory cell turns off in the first operation and the third memory cell turns on in the third operation.

13. A semiconductor memory device comprising:

a memory cell set including a first memory cell and a second memory cell; and

a bit line capable of being electrically coupled to the first memory cell and the second memory cell of the memory cell set,

wherein the first memory cell faces the second memory cell with a semiconductor layer interposed therebetween,

the semiconductor memory device is configured to perform a read operation with the memory cell set, the read operation including a first operation to read data from one of the first memory cell and the second memory cell, and a second operation to read data from remaining one of the first memory cell and the second memory cell,

when the first memory cell of the memory cell set is selected, the semiconductor memory device is configured to:

perform the first operation to read data from the second memory cell, and

perform, after the first operation, the second operation to read data from the first memory cell, and

when the second memory cell of the memory cell set is selected, the semiconductor memory device is configured to perform the second operation to read data from the second memory cell without the first operation.

14. The device according to claim 13 , further comprising:

a first word line coupled to the first memory cell;

a second word line coupled to the second memory cell; and

a sense amplifier configured to determine data read on the bit line from one of the first memory cell and the second memory cell,

wherein when the first memory cell is selected in the read operation, the semiconductor memory device is configured to:

perform the first operation in which a first voltage is applied to the first word line and a second voltage higher than the first voltage is applied to the second word line, and

perform the second operation in which a third voltage higher than the first voltage and a fourth voltage different from the third voltage are applied to the first word line and a fifth voltage lower than the second to the fourth voltage is applied to the second word line, and

wherein the first voltage and the fifth voltage turn off a memory cell.

15. The device according to claim 13 , further comprising:

a first word line;

a second word line; and

a third word line,

wherein the memory cell set includes a first memory cell set and a second memory cell set,

the bit line includes a first bit line and a second bit line,

a first memory cell of the first memory cell set and a first memory cell of the second memory cell set are coupled to the first word line,

a second memory cell of the first memory cell set is coupled to the second word line,

a second memory cell of the second memory cell set is coupled to the third word line, and

in the read operation, the semiconductor memory device is configured to:

perform the first operation and the second operation with the first memory cell set, when the first memory cell of the first memory cell set is selected,

perform the second operation with the first memory cell set without the first operation, when the second memory cell of the first memory cell set is selected,

perform the second operation with the second memory cell set without the first operation, when the first memory cell of the second memory cell set is selected, and

perform the first operation and the second operation with the second memory cell set, when the second memory cell of the second memory cell set is selected.

16. The device according to claim 15 , wherein data is written into the first memory cell of the first memory cell set and the first memory cell of the second memory cell set in parallel,

data is written into the second memory cell of the first memory cell set after the data is written into the first memory cell of the first memory cell set and the first memory cell of the second memory cell set, and

data is written into the second memory cell of the second memory cell set before the data is written into the first memory cell of the first memory cell set and the first memory cell of the second memory cell set.

17. The device according to claim 13 , further comprising: