Timer management for network devices

1. A method comprising:

maintaining, by a timer manager of a device, a plurality of successive wheels available to be included in traversal paths for timers running on the device, each of the wheels representing a queue of timers, and each of the wheels having a different, corresponding time delay (TO) values for queuing a timer;

responsive to a request for a timer, determining, by the timer manager of the device, a total traversal time with respect to the timer;

selecting, by the timer manager of the device, from the plurality of wheels, a subset of wheels such that a sum of the respective TO values of the selected subset of wheels is within a predetermined margin of error with respect to the total traversal time for the timer; and

sequencing, by the timer manager of the device, the selected subset of wheels based on the respective TO values of the selected subset of wheels to form a traversal path with respect to the timer.

2. The method of claim 1 , wherein selecting the subset of wheels comprises:

forming, by the timer manager of the device, a bitmask that corresponds to a binary value representing the total traversal time;

identifying, by the timer manager of the device, one or more significant bits in the bitmask; and

identifying, by the timer manager of the device, in the plurality of wheels, each respective wheel that corresponds to each respective significant bit in the bitmask.

3. The method of claim 2 , further comprising:

placing, by the timer manager of the device, the timer at an end of a first wheel of the traversal path;

determining, by the timer manager of the device, that the timer has graduated from the first wheel of the traversal path;

in response to determining that the timer has graduated from the first wheel of the traversal path, removing, by the timer manager of the device, a most significant bit from the bitmask to form an updated bitmask, the most significant bit corresponding to the first wheel in the bitmask.

4. The method of claim 3 , further comprising:

determining one or more alternate traversal times, each respective alternate traversal time being within a predetermined margin of error with respect to the traversal time;

determining, by the timer manager of the device, one or more remaining traversal time options that each represent a respective difference between the respective alternate traversal time and the respective TO value of the first wheel of the traversal path;

selecting, by the timer manager of the device, a remaining traversal time for the timer from the remaining traversal time options; and

based on the remaining traversal time selected for the timer, inverting, by the timer manager of the device, one or more bits of the updated bitmask to form an altered traversal path with respect to the timer.

5. The method of claim 4 , wherein inverting the one or more bits comprises:

changing, by the timer manager of the device, a least significant bit of the bitmask to a zero (0) value in the updated bitmask; and

assigning, by the timer manager of the device, a new least significant bit of the updated bitmask by changing a zero (0) value of the bitmask to a one (1) value in the updated bitmask.

6. The method of claim 3 , further comprising:

detecting, based on an actual performance of the timer in the first wheel of the traversal path, a delay with respect to the timer and the first wheel of the traversal path;

determining, by the timer manager of the device, one or more remaining traversal time options that each represent a respective difference between a respective alternate traversal time and a sum of the respective TO value of the first wheel of the traversal path and the detected delay; and

selecting, by the timer manager of the device, a remaining traversal time for the timer from the remaining traversal time options; and

based on the remaining traversal time selected for the timer, inverting, by the timer manager of the device, one or more bits of the updated bitmask to form an altered traversal path with respect to the timer.

7. The method of claim 1 , wherein sequencing the selected subset of wheels based on the respective TO values of the selected subset of wheels comprises sequencing, by the timer manager of the device, the selected subset of wheels according to a descending order of the respective TO values of the selected subset of wheels to form a traversal path with respect to the timer.

8. A device comprising:

a memory configured to store a plurality of successive wheels available to be included in traversal paths for timers running on the device, each of the wheels representing a queue of timers, and each of the wheels having a different, corresponding time delay (TO) values for queuing a timer; and

processing circuitry in communication with the memory, the processing circuitry being configured to:

determine, in response to a request for a timer, a total traversal time with respect to the timer;

select, from the plurality of wheels stored to the memory, a subset of wheels such that a sum of the respective TO values of the selected subset of wheels is within a predetermined margin of error with respect to the total traversal time for the timer; and

sequence the selected subset of wheels based on the respective TO values of the selected subset of wheels to form a traversal path with respect to the timer.

9. The device of claim 8 , wherein, to select the subset of wheels, the processing circuitry is configured to:

form a bitmask that corresponds to a binary value representing the total traversal time;

identify one or more significant bits in the bitmask; and

identify, in the plurality of wheels, each respective wheel that corresponds to each respective significant bit in the bitmask.

10. The device of claim 8 , wherein the processing circuitry is further configured to:

place the timer at an end of a first wheel of the traversal path;

determine that the timer has graduated from the first wheel of the traversal path;

in response to the determination that the timer has graduated from the first wheel of the traversal path, remove a most significant bit from the bitmask to form an updated bitmask, the most significant bit corresponding to the first wheel in the bitmask.

11. The device of claim 10 , wherein the processing circuitry is further configured to:

determine one or more alternate traversal times, each respective alternate traversal time being within a predetermined margin of error with respect to the traversal time;

determine one or more remaining traversal time options that each represent a respective difference between the respective alternate traversal time and the respective TO value of the first wheel of the traversal path;

select a remaining traversal time for the timer from the remaining traversal time options; and

invert, based on the remaining traversal time selected for the timer, one or more bits of the updated bitmask to form an altered traversal path with respect to the timer.

12. The device of claim 11 , wherein to invert the one or more bits, the processing circuitry is configured to:

change a least significant bit of the bitmask to a zero (0) value in the updated bitmask; and

assign a new least significant bit of the updated bitmask by changing a zero (0) value of the bitmask to a one (1) value in the updated bitmask.

13. The device of claim 10 , wherein the processing circuitry is further configured to:

detect, based on an actual performance of the timer in the first wheel of the traversal path, a delay with respect to the timer and the first wheel of the traversal path;

determine one or more remaining traversal time options that each represent a respective difference between a respective alternate traversal time and a sum of the respective TO value of the first wheel of the traversal path and the detected delay; and

select a remaining traversal time for the timer from the remaining traversal time options; and

invert, based on the remaining traversal time selected for the timer, one or more bits of the updated bitmask to form an altered traversal path with respect to the timer.

14. The device of claim 8 , wherein to sequence the selected subset of wheels based on the respective TO values of the selected subset of wheels, the processing circuitry is configured to sequence the selected subset of wheels according to a descending order of the respective TO values of the selected subset of wheels.

15. The device of claim 8 , wherein the processing circuitry comprises at least a portion of an application-specific integrated circuit (ASIC).

16. The device of claim 8 , wherein the processing circuitry comprises discrete logic circuitry.

17. The device of claim 8 , wherein the processing circuitry comprises fixed function circuitry.

18. The device of claim 8 , wherein the processing circuitry comprises an application specific integrated circuit (ASIC).

19. A non-transitory computer-readable storage medium encoded with instructions that, when executed, cause processing circuitry of a device to:

store, to a memory, a plurality of successive wheels available to be included in traversal paths for timers running on the device, each of the wheels representing a queue of timers, and each of the wheels having a different, corresponding time delay (TO) values for queuing a timer;

determine, in response to a request for a timer, a total traversal time with respect to the timer;

select, from the plurality of wheels stored to a memory, a subset of wheels such that a sum of the respective TO values of the selected subset of wheels is within a predetermined margin of error with respect to the total traversal time for the timer; and

sequence the selected subset of wheels based on the respective TO values of the selected subset of wheels to form a traversal path with respect to the timer.

20. The non-transitory computer-readable storage medium of claim 19 , wherein the instructions that cause the processing circuitry to select the subset of wheels comprise instructions that, when executed, cause the processing circuitry to:

form a bitmask that corresponds to a binary value representing the total traversal time;

identify one or more significant bits in the bitmask; and

identify, in the plurality of wheels, each respective wheel that corresponds to each respective significant bit in the bitmask.

21. The non-transitory computer-readable storage medium of claim 19 , further encoded with instructions that, when executed, cause the processing circuitry to:

place the timer at an end of a first wheel of the traversal path;

determine that the timer has graduated from the first wheel of the traversal path;

in response to the determination that the timer has graduated from the first wheel of the traversal path, remove a most significant bit from the bitmask to form an updated bitmask, the most significant bit corresponding to the first wheel in the bitmask.

22. The non-transitory computer-readable storage medium of claim 21 , further encoded with instructions that, when executed, cause the processing circuitry to:

determine one or more alternate traversal times, each respective alternate traversal time being within a predetermined margin of error with respect to the traversal time;

determine one or more remaining traversal time options that each represent a respective difference between the respective alternate traversal time and the respective TO value of the first wheel of the traversal path;

select a remaining traversal time for the timer from the remaining traversal time options; and

invert, based on the remaining traversal time selected for the timer, one or more bits of the updated bitmask to form an altered traversal path with respect to the timer.

23. The non-transitory computer-readable storage medium of claim 22 , wherein the instructions that cause the processing circuitry to invert the one or more bits comprise instructions that, when executed, cause the processing circuitry to:

change a least significant bit of the bitmask to a zero (0) value in the updated bitmask; and

assign a new least significant bit of the updated bitmask by changing a zero (0) value of the bitmask to a one (1) value in the updated bitmask.

24. The non-transitory computer-readable storage medium of claim 21 , further encoded with instructions that, when executed, cause the processing circuitry to:

detect, based on an actual performance of the timer in the first wheel of the traversal path, a delay with respect to the timer and the first wheel of the traversal path;

determine one or more remaining traversal time options that each represent a respective difference between a respective alternate traversal time and a sum of the respective TO value of the first wheel of the traversal path and the detected delay; and

select a remaining traversal time for the timer from the remaining traversal time options; and

invert, based on the remaining traversal time selected for the timer, one or more bits of the updated bitmask to form an altered traversal path with respect to the timer.

25. The non-transitory computer-readable storage medium of claim 19 , wherein the instructions that cause the processing circuitry to sequence the selected subset of wheels based on the respective TO values of the selected subset of wheels comprise instructions that, when executed, cause the processing circuitry to sequence the selected subset of wheels according to a descending order of the respective TO values of the selected subset of wheels.

26. An apparatus comprising:

means for maintaining a plurality of successive wheels available to be included in traversal paths for timers running on the device, each of the wheels representing a queue of timers, and each of the wheels having a different, corresponding time delay (TO) values for queuing a timer;

means for determining, in response to a request for a timer, a total traversal time with respect to the timer;

means for selecting, from the plurality of wheels, a subset of wheels such that a sum of the respective TO values of the selected subset of wheels is within a predetermined margin of error with respect to the total traversal time for the timer; and

means for sequencing the selected subset of wheels according to a descending order of the respective TO values of the selected subset of wheels to form a traversal path with respect to the timer.