Neural network accelerator with parameters resident on chip
One embodiment of an accelerator includes a computing unit; a first memory bank for storing input activations and a second memory bank for storing parameters used in performing computations, the second memory bank configured to store a sufficient amount of the neural network parameters on the computing unit to allow for latency below a specified level with throughput above a specified level. The computing unit includes at least one cell comprising at least one multiply accumulate (“MAC”) operator that receives parameters from the second memory bank and performs computations. The computing unit further includes a first traversal unit that provides a control signal to the first memory bank to cause an input activation to be provided to a data bus accessible by the MAC operator. The computing unit performs computations associated with at least one element of a data array, the one or more computations performed by the MAC operator.
1. An accelerator for accelerating tensor computations, comprising:
a computing unit comprising:
a memory bank comprising a register, the memory bank configured for storing a sufficient amount of machine learning parameters on the computing unit to allow for latency below a specified level with throughput above a specified level for a given machine learning model;
at least one cell comprising at least one operator that receives the stored machine learning parameters from the memory bank and performs one or more computations; and
wherein the one or more computations are associated with at least one element of a data array, the one or more computations being performed by the at least one operator and comprising, in part, a multiply operation of an input parameter and a parameter received from the memory bank, and wherein the memory bank, a tensor traversal unit in data communication with another memory bank, and the at least one operator are located on a same die.
2. The accelerator of claim 1 , wherein the memory bank is configured to store more than 100,000 parameters.
3. The accelerator of claim 1 , wherein the memory bank is configured to store more than 1,000,000 parameters.
4. The accelerator of claim 1 , wherein the memory bank is configured to store more than 100,000,000 parameters.
5. The accelerator of claim 1 , wherein the memory bank comprises SRAM.
6. The accelerator of claim 1 , further comprising a data bus accessible by the at least one operator.
7. The accelerator of claim 6 , wherein the tensor traversal unit is configured to provide a control signal to the other memory bank to cause an input activation to be provided to the data bus accessible by the at least one operator.
8. The accelerator of claim 7 , wherein the other memory bank is configured to provide the data bus one-by-one broadcast of input activations such that each of the at least one operator receives a respective input activation.