IP Library Granted Patent US 11,190,235
Granted Patent B2
US 11,190,235 · App. 16/569,630 · Granted Nov 30, 2021

Low-power differential data transmission systems and methods

Inventors: Aswani Tadinada (Serilingampalli, IN); Venkatasuryam Issa (Serilingampalli, IN); Jens Kristian Poulsen (Kitchener, CA)
Assignee: SYNAPTICS INCORPORATED
H04B3/38H04B3/14H04B3/46H04B3/542H04B3/56
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Quick Facts
Patent No.
US 11,190,235
App. No.
16/569,630
Granted
Nov 30, 2021
Kind
B2
Abstract

Systems and methods for differential data transmission using an unterminated transmission line comprise a plurality of switches configured to control a differential voltage output on a pair of output lines, wherein the plurality of switches have a first state in which a high voltage is output on a first of the pair of output lines and a low voltage is output on a second of the pair of output lines, and wherein the plurality of switches have a second state in which the low voltage is output on the first of the pair of output lines and the high voltage is output on the second of the pair of output lines. A transition switch with an output impedance equal to that of the output lines will discharge the lines during a state transition so as to reduce to power consumption associated with changing states of the transmission line.

Claims (47)

1. A circuit comprising:

a differential data transmitter comprising a plurality of switches configured to control a differential voltage output on an unterminated transmission line comprising a pair of output lines, wherein the plurality of switches have a first state in which a high voltage is output on a first of the output lines and a low voltage is output on a second of the output lines, and wherein the plurality of switches have a second state in which the low voltage is output on the first of the output lines and the high voltage is output on the second output of the output lines; and

a transition switch configured to discharge the output lines during a state transition,

wherein the transition switch is coupled between the pair of output lines and has an output impedance substantially matched to the pair of output lines.

2. The circuit of claim 1 , wherein the transition switch is further configured to close the transition switch for a certain duration to bring the voltages of the pair of output lines to approximately one-half a total voltage on the pair of output lines.

3. The circuit of claim 1 , wherein when the transition switch is activated, a voltage fall on one of the pair of output lines is approximately equal to a voltage rise on the other of the pair of output lines.

4. The circuit of claim 1 , wherein the differential data transmitter comprises matching resistors provided in series with each of the switches.

5. The circuit of claim 1 , wherein each of the plurality of switches comprises an NMOS transistor; and wherein a data level is maintained at a lower voltage than a threshold voltage for the NMOS transistors thereby reducing leakage.

6. The circuit of claim 1 , wherein the differential data transmitter is configured to output at a third voltage level.

7. The circuit of claim 1 , further comprising a capacitor coupled between the pair of output lines, wherein the capacitor is a piezoelectric capacitor.

8. A circuit comprising:

a differential data transmitter comprising a plurality of switches configured to control a differential voltage output on an unterminated transmission line comprising a pair of output lines, wherein the plurality of switches have a first state in which a high voltage is output on a first of the output lines and a low voltage is output on a second of the output lines, and wherein the plurality of switches have a second state in which the low voltage is output on the first of the output lines and the high voltage is output on the second output of the output lines; and

a transition switch configured to discharge the output lines during a state transition, wherein the transition switch is closed for a duration that is at least two times a delay of signals from a start of the unterminated transmission line to an end of the unterminated transmission line thereby discharging the unterminated transmission line before sending out a symbol with a new value.

9. A circuit comprising:

a differential data transmitter comprising a plurality of switches configured to control a differential voltage output on an unterminated transmission line comprising a pair of output lines, wherein the plurality of switches have a first state in which a high voltage is output on a first of the output lines and a low voltage is output on a second of the output lines, and wherein the plurality of switches have a second state in which the low voltage is output on the first of the output lines and the high voltage is output on the second output of the output lines; and

a transition switch configured to discharge the output lines during a state transition,

wherein the differential data transmitter comprises an H-bridge driver circuit; wherein the plurality of switches comprises a plurality of transistor switches; and wherein the transition switch comprises a shorting switch having a plurality of transistors configured to function as a transmission gate.

10. A method comprising:

providing a differential data transmitter comprising a plurality of switches;

controlling a differential voltage output on an unterminated transmission line comprising a pair of output lines including transitioning between a first state and a second state;

selectively entering the first state in which a high voltage is output on a first of the pair of output lines and a low voltage is output on a second of the pair of output lines;

selectively entering the second state in which the low voltage is output on the first of the pair of output lines and the high voltage is output on the second of the pair of output lines;

activating a transition switch to redistribute charges between the pair of output lines during a state transition

providing an H-bridge driver circuit; and

operating a transmission gate comprising a shorting switch having a plurality of transistors.

11. The method of claim 10 , further comprising absorbing the charges by closing the transition switch for a duration to bring the voltages of the pair of output lines to approximately one-half a total voltage on the pair of output lines.

12. The method of claim 10 , wherein the transition switch is closed for a duration that is at least equal to two times a propagation time from input to output of the transmission line.

13. The method of claim 10 , further comprising:

coupling the transition switch between the pair of output lines; and

configuring the transition switch through a series resistor such that an output resistance of the transition switch and the series resistor is approximately equal to an input impedance of the transmission line.

14. The method of claim 10 , further comprising activating the transition switch to discharge the transmission line when the data changes value.

15. The method of claim 10 , further comprising providing matching resistors in series with each of the switches.

16. The method of claim 10 , further comprising operating the differential data transmitter to output at a third voltage level.

17. A method comprising:

providing a differential data transmitter comprising a plurality of switches;

controlling a differential voltage output on an unterminated transmission line comprising a pair of output lines including transitioning between a first state and a second state;

selectively entering the first state in which a high voltage is output on a first of the pair of output lines and a low voltage is output on a second of the pair of output lines;

selectively entering the second state in which the low voltage is output on the first of the pair of output lines and the high voltage is output on the second of the pair of output lines;

activating a transition switch to redistribute charges between the pair of output lines during a state transition;

providing a plurality of NMOS transistors; and maintaining an input voltage at less than a threshold voltage of the NMOS transistors, thereby reducing leakage for the differential data transmitter.

18. A method comprising:

providing a differential data transmitter comprising a plurality of switches;

controlling a differential voltage output on an unterminated transmission line comprising a pair of output lines including transitioning between a first state and a second state;

selectively entering the first state in which a high voltage is output on a first of the pair of output lines and a low voltage is output on a second of the pair of output lines;

selectively entering the second state in which the low voltage is output on the first of the pair of output lines and the high voltage is output on the second of the pair of output lines;

activating a transition switch to redistribute charges between the pair of output lines during a state transition; and

providing a piezoelectric driver between the pair of output lines.

Assignments (2)
SECURITY INTEREST Recorded Feb 14, 2020
From: SYNAPTICS INCORPORATED
To: WELLS FARGO BANK, NATIONAL ASSOCIATION
Reel/Frame 051936/0103 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 3, 2019
From: TADINADA, ASWANI; ISSA, VENKATASURYAM SETTY; POULSEN, JENS KRISTIAN
To: SYNAPTICS INCORPORATED
Reel/Frame 050619/0181 →