IP Library Granted Patent US 10,828,891
Granted Patent B2
US 10,828,891 · App. 16/570,321 · Granted Nov 10, 2020

Ink jet head and ink jet printer

Inventor: Teruyuki Hiyoshi (Izunokuni Shizuoka, JP)
Assignee: TOSHIBA TEC KABUSHIKI KAISHA
B41J2/0457B41J2/0451B41J2/04541B41J2/04548B41J2/04581
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Quick Facts
Patent No.
US 10,828,891
App. No.
16/570,321
Granted
Nov 10, 2020
Kind
B2
Abstract

An ink jet head includes an actuator, a driver IC, a first capacitor, a second capacitor, and a fuse. The actuator is configured to cause ink to be discharged from nozzles. The driver IC is configured to drive the actuator. The first capacitor is connected between a ground line and a first node of a power supply line connected to the driver IC. The second capacitor is connected between a ground line and a second node of the power supply line. A capacitance of the second capacitor is less than a capacitance of the first capacitor. The fuse is on the power supply line between the first node and the second node.

Claims (58)

1. An ink jet head, comprising:

an actuator configured to cause ink to be discharged from nozzles;

a driver IC connected to a power supply line and configured to drive the actuator;

a first capacitor connected between a ground line and a first node of the power supply line;

a second capacitor connected between the ground line and a second node of the power supply line, the second node being between the first node and the driver IC, a capacitance of the second capacitor being smaller than a capacitance of the first capacitor; and

a fuse on the power supply line between the first node and the second node.

2. The ink jet head according to claim 1 , wherein the ground line is connected to the driver IC, and the first capacitor is connected to a third node of the ground line and the second capacitor is connected to a fourth node of the ground line, and the fourth node is between the third node and the driver IC.

3. The ink jet head according to claim 1 , wherein the capacitance of the second capacitor is in a range of 8% to 25% of the capacitance of the first capacitor.

4. The ink jet head according to claim 1 , wherein the capacitance of the first capacitor and the capacitance of the second capacitor are both variable based on a bias voltage respectively applied thereto, and the capacitance of the second capacitor when being biased is in a range of 9% to 27% of the capacitance of the first capacitor when being biased.

5. The ink jet head according to claim 1 , wherein the driver IC includes:

a logic circuit configured to generate a drive signal;

a level shifter configured to shift a voltage level of the drive signal to generate a level-shifted drive signal; and

a driver configured to operate based on power supplied from the power supply line and output, based on the level-shifted drive signal, a signal of one of a first level, based on a voltage level of the power supply line, and a second level based on a ground voltage level.

6. The ink jet head according to claim 5 , wherein

the logic circuit is configured to operate based on power supplied from a second power supply line different from the power supply line, and

the level shifter is configured to operate based on power supplied from a third power supply line different from the power supply line and the second power supply line.

7. The ink jet head according to claim 1 , further comprising:

a head substrate, wherein the first capacitor, the second capacitor, the fuse, and at least a part of the power supply line are provided on the head substrate.

8. An ink jet head, comprising:

an actuator configured to cause ink to be discharged from nozzles;

a driver IC configured to drive the actuator;

a power supply line connected to the driver IC;

a ground line connected to the driver IC; and

a protection circuit including:

a first capacitor connected between the ground line and a first node of the power supply line;

a second capacitor connected between the ground line and a second node of the power supply line, the second node being between the first node and the driver IC, a capacitance of the second capacitor being less than a capacitance of the first capacitor; and

a fuse on the power supply line between the first node and the second node.

9. The ink jet head according to claim 8 , wherein the first capacitor is connected to a third node of the ground line and the second capacitor is connected to a fourth node, the fourth node being between the third node and the driver IC.

10. The ink jet head according to claim 8 , wherein the capacitance of the second capacitor is in a range of 8% to 25% of the capacitance of the first capacitor.

11. The ink jet head according to claim 8 , wherein the capacitance of the first capacitor and the capacitance of the second capacitor are both variable based on a bias voltage applied thereto, and the capacitance of the second capacitor when being biased is in a range of 9% to 27% of the capacitance of the first capacitor when being biased.

12. The ink jet head according to claim 8 , wherein the driver IC includes:

a logic circuit configured to generate a drive signal;

a level shifter configured to shift a voltage level of the drive signal to generate a level-shifted drive signal; and

a driver configured to operate based on power supplied from the power supply line and output, based on the level-shifted drive signal, a signal of one of a first level based on a voltage level of the power supply line and a second level based on a ground voltage level.

13. The ink jet head according to claim 12 , wherein

the logic circuit is configured to operate based on power supplied from a second power supply line different from the power supply line, and

the level shifter is configured to operate based on power supplied from a third power supply line different from the power supply line and the second power supply line.

14. The ink jet head according to claim 8 , further comprising:

a head substrate, wherein the first capacitor, the second capacitor, the fuse, at least a part of the power supply line, and at least a part of the ground line are provided on the head substrate.

15. An ink jet printer, comprising:

a conveyance motor configured to convey a sheet;

an ink jet head configured to discharge ink onto the sheet; and

a head controller configured to supply power and a control signal to the ink jet head, wherein the ink jet head comprises:

an actuator configured to cause ink to be discharged from nozzles;

a driver IC configured to drive the actuator;

a first capacitor connected between a ground line and a first node of a power supply line connected to the driver IC;

a second capacitor connected between the ground line and a second node of the power supply line, the second node being between the first node and the driver IC, a capacitance of the second capacitor being less than a capacitance of the first capacitor; and

a fuse on the power supply line between the first node and the second node.

16. The ink jet printer according to claim 15 , wherein the first capacitor is connected to a third node of the ground line and the second capacitor is connected to a fourth node of the ground line, the fourth node being between the third node and the driver IC.

17. The ink jet printer according to claim 15 , wherein the capacitance of the second capacitor is in a range of 8% to 25% of the capacitance of the first capacitor.

18. The ink jet printer according to claim 15 , wherein the capacitance of the first capacitor and the capacitance of the second capacitor are both variable based on a bias voltage applied thereto, and the capacitance of the second capacitor when being biased is in a range of 9% to 27% of the capacitance of the first capacitor when being biased.

19. The ink jet printer according to claim 15 , wherein the driver IC includes:

a logic circuit configured to generate a drive signal;

a level shifter configured to shift a voltage level of the drive signal to generate a level-shifted drive signal; and

a driver configured to operate based on power supplied from the power supply line and output, based on the level-shifted drive signal, a signal of one of a first level, based on a voltage level of the power supply line, and a second level, based on a ground voltage level.

20. The ink jet printer according to claim 19 , wherein

the logic circuit is configured to operate based on power supplied from a second power supply line different from the power supply line, and

the level shifter is configured to operate based on power supplied from a third power supply line different from the power supply line and the second power supply line.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 7, 2024
From: TOSHIBA TEC KABUSHIKI KAISHA
To: RISO TECHNOLOGIES CORPORATION
Reel/Frame 068493/0970 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 13, 2019
From: HIYOSHI, TERUYUKI
To: TOSHIBA TEC KABUSHIKI KAISHA
Reel/Frame 050370/0023 →
Priority Claims (1)
JP 2018-238572 · Dec 20, 2018 · national
Continuity (1)
Related Publication 20200198326A1 · Jun 25, 2020