Circuit, chip and semiconductor device

1. A circuit, comprising: a time-to-digital converter(TDC), configured to receive a first signal having an identification and a first frequency, and output a digital signal associated with the identification of the first signal; and an evaluation circuit, coupled to the TDC and a phase-locked loop (PLL) external to the circuit, wherein the evaluation circuit is configured to receive the digital signal, and output a signal indicating a parameter associated with the digital signal to the PLL.

2. The circuit of claim 1 , wherein the identification comprises a duty cycle.

3. The circuit of claim 2 , wherein a level of the parameter corresponds to a range within which the duty cycle falls.

4. The circuit of claim 1 , further comprising: a frequency divider coupled to the TDC to provide a second signal having a second frequency to the TDC.

5. The circuit of claim 4 , wherein the digital signal is generated based on the second signal from the frequency divider.

6. The circuit of claim 4 , wherein the digital signal is generated by sampling the first signal by means of the second signal.

7. The circuit of claim 1 , wherein the TDC comprises:

a first buffer having a first input and a first output;

a second buffer having a second input coupled to the first output of the first buffer, and a second output;

a first sampling circuit having a first input coupled to the first output of the first buffer, a second input, and a first output; and

a second sampling circuit having a third input coupled to the second output of the second buffer, a fourth input coupled to the second input of the first sampling circuit, and a second output.

8. The circuit of claim 7 , wherein the first input of the first buffer is configured to receive the first signal having the identification and the first frequency.

9. The circuit of claim 8 , further comprising a frequency divider, wherein the second input of the first sampling circuit is coupled to the frequency divider to receive a second signal having a second frequency.

10. The circuit of claim 9 , wherein the first output of the first sampling circuit provides a first voltage level in accordance with the first signal and the second signal.

11. The circuit of claim 10 , wherein the second output of the second sampling circuit provides a second voltage level in accordance with a signal received from the second output of the second buffer and the second signal.

12. The circuit of claim 11 , wherein the TDC outputs the first voltage level and the second voltage level to the evaluation circuit.

13. The circuit of claim 2 , wherein the evaluation circuit is configured to evaluate the duty cycle by determining a rising edge and a falling edge of the digital signal.

14. The circuit of claim 1 , wherein the evaluation circuit is configured to evaluate the identification, based on the digital signal, to provide an evaluated identification.

15. The circuit of claim 14 , wherein the evaluation circuit is configured to determine the parameter based on the evaluated identification.

16. The circuit of claim 15 , wherein the identification is evaluated based on a transition between a first voltage level and a second voltage level of the digital signal.

17. A phase-locked loop (PLL), comprising:

a time-to-digital converter (TDC);

an evaluation circuit coupled to the TDC; and

an output divider (OD), coupled to the evaluation circuit and a device under test (DUT) external to the PLL;

wherein the TDC is configured to receive a first signal having an identification and a first frequency, and output a digital signal associated with the identification of the first signal to the evaluation circuit; the identification comprises a duty cycle.

18. The PLL of claim 17 , wherein the evaluation circuit is configured to receive a predetermined quantity of voltage levels in a period of time.

19. A semiconductor device, comprising:

a time-to-digital converter (TDC), configured to receive a first signal having a first frequency and an identification;

an evaluation circuit coupled to the TDC;

an output divider (OD) coupled to the evaluation circuit; and

a device under test (DUT) coupled to the output divider;

wherein the OD is configured to output a second signal having a second frequency associated with the identification to the DUT.

20. The PLL of claim 17 , wherein a test pattern is coupled to the OD to control operation the OD; when the second frequency is changed from a first frequency level to a second frequency level different from the first frequency level, the test pattern is kept the same.