IP Library Granted Patent US 10,867,569
Granted Patent B2
US 10,867,569 · App. 16/575,002 · Granted Dec 15, 2020

Display device

Inventors: Genshirou Kawachi (Hyogo, JP); Kuniaki Amano (Hyogo, JP); Ryutaro Oke (Hyogo, JP); Daisuke Kajita (Hyogo, JP)
Assignee: Panasonic Liquid Crystal Display Co., Ltd.
G09G3/3648G02F1/1368G02F1/13454G02F1/136286G09G3/3685H01L27/124G09G2300/0439
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Quick Facts
Patent No.
US 10,867,569
App. No.
16/575,002
Granted
Dec 15, 2020
Kind
B2
Abstract

A display device includes: pixel transistors electrically connected to the respective source lines and the respective gate lines; a monitor transistor in which a lead-out wiring of a drain electrode is electrically connected to a first external terminal, a lead-out wiring of a gate electrode is electrically connected to a second external terminal, and a lead-out wiring of a source electrode is electrically connected to a third external terminal; a reference transistor in which a lead-out wiring of a drain electrode is electrically connected to a fourth external terminal, a lead-out wiring of a gate electrode is electrically connected to a fifth external terminal, and a lead-out wiring of a source electrode is electrically connected to a sixth external terminal; and a detector electrically connected to the third external terminal and the sixth external terminal to detect a shift amount of a threshold voltage of the monitor transistor.

Claims (27)

1. A display device comprising:

a plurality of source lines;

a plurality of gate lines;

a source driver that supplies a data signal to each of the plurality of source lines;

a gate driver that supplies a gate signal to each of the plurality of gate lines;

a plurality of pixel transistors electrically connected to the respective source lines and the respective gate lines;

a monitor transistor in which a lead-out wiring of a drain electrode is electrically connected to a first external terminal, a lead-out wiring of a gate electrode is electrically connected to a second external terminal, and a lead-out wiring of a source electrode is electrically connected to a third external terminal;

a reference transistor in which a lead-out wiring of a drain electrode is electrically connected to a fourth external terminal, a lead-out wiring of a gate electrode is electrically connected to a fifth external terminal, and a lead-out wiring of a source electrode is electrically connected to a sixth external terminal; and

a detector that is electrically connected to the third external terminal and the sixth external terminal to detect a shift amount of a threshold voltage of the monitor transistor.

2. The display device according to claim 1 , wherein a first mode in which an image is displayed and a second mode in which the shift amount of the threshold voltage of the monitor transistor is detected are included,

in the first mode, the data signal is applied to the drain electrode of the monitor transistor, the gate signal is applied to the gate electrode of the monitor transistor, and the lead-out wirings of the drain electrode and the gate electrode of the reference transistor are connected to a constant voltage source, and

in the second mode, a predetermined voltage is applied to the drain electrode of each of the monitor transistor and the reference transistor, the lead-out wire of the gate electrode of each of the monitor transistor and the reference transistor is connected to a constant voltage source, and the detector detects the shift amount based on a drain current of each of the monitor transistor and the reference transistor.

3. The display device according to claim 1 , further comprising a controller that applies a correction voltage to the plurality of pixel transistors based on the shift amount,

wherein the controller applies the correction voltage to the gate electrode of each of the plurality of pixel transistors when the shift amount is larger than a first reference voltage.

4. The display device according to claim 3 , wherein the controller sets an application period of the correction voltage longer with increasing shift amount.

5. The display device according to claim 3 , wherein a signal waveform of the correction voltage has an inclined rising period and an inclined falling period.

6. The display device according to claim 3 , wherein the controller outputs a control signal to the source driver and the gate driver when the shift amount is larger than a first reference voltage,

the source driver outputs a common voltage to the respective source lines only for a predetermined period when the source driver receives the control signal, and

the gate driver outputs the correction voltage to the respective gate lines only for the predetermined period when the gate driver receives the control signal.

7. The display device according to claim 3 , wherein the processing of applying the correction voltage to the gate electrode of each of the plurality of pixel transistors using the controller is performed after an operation to power off the display device is received.

8. The display device according to claim 3 , wherein in processing of applying the correction voltage to the gate electrode of each of the plurality of pixel transistors using the controller, the controller sequentially supplies the correction voltage to the plurality of gate lines.

9. The display device according to claim 1 , wherein the plurality of source lines, the plurality of gate lines, the source driver, the gate driver, the plurality of pixel transistors, the monitor transistor, and the reference transistor are provided in a display panel, and

the detector is provided outside the display panel.

10. The display device according to claim 9 , wherein the monitor transistor and the reference transistor are disposed close to each other in a non-display region of the display panel.

11. The display device according to claim 1 , wherein a first mode in which an image is displayed and a second mode in which the shift amount of the threshold voltage of the monitor transistor is detected are included,

in the first mode, the data signal is applied to the drain electrode of the monitor transistor, the gate signal is applied to the gate electrode of the monitor transistor, and the lead-out wirings of the drain electrode and the gate electrode of the reference transistor are connected to a constant voltage source, and

in the second mode, the drain electrode and the gate electrode of the monitor transistor are electrically connected to each other while electrically connected to a constant current source, the drain electrode and the gate electrode of the reference transistor are electrically connected to each other while electrically connected to the constant current source, and the detector detects the shift amount based on a drain voltage of each of the monitor transistor and the reference transistor.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 18, 2023
From: PANASONIC LIQUID CRYSTAL DISPLAY CO., LTD.
To: PANASONIC INTELLECTUAL PROPERTY CORPORATION OF AMERICA
Reel/Frame 064292/0775 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 25, 2019
From: KAWACHI, GENSHIROU; AMANO, KUNIAKI; OKE, RYUTARO; KAJITA, DAISUKE
To: PANASONIC LIQUID CRYSTAL DISPLAY CO., LTD.
Reel/Frame 051110/0914 →
Priority Claims (1)
JP 2017-057040 · Mar 23, 2017 · national
Continuity (2)
Continuation PCTJP2018003188 · Jan 31, 2018
Related Publication 20200013358A1 · Jan 9, 2020