Memory system and operating method thereof

1. A method for operating a memory system including a memory device and a controller which controls the memory device, the method comprising:

queuing a plurality of commands input from an external device in a host command queue;

identifying a target command among a plurality of commands queued in the host command queue;

controlling a transmission of the target command from the host command queue to a memory command queue based on an estimated power consumption of the memory device;

controlling the transmission of the target command from the host command queue to the memory command queue based on an estimated de-queuing time of the memory command queue; and

performing an operation corresponding to the target command.

2. The method according to claim 1 , wherein the controlling the transmission includes:

comparing an estimated power of the memory device with a power limit; and

transmitting the target command from the host command queue to the memory command queue in response to the estimated power being smaller than the power limit.

3. The method according to claim 2 , wherein the checking the estimated de-queuing time includes:

transmitting the target command from the host command queue to the memory command queue in response to the estimated power being larger than or equal to the power limit and the estimated de-queuing time smaller than a predetermined threshold value; and

deferring the transmitting the target command from the host command queue to the memory command queue in response to the estimated power being larger than or equal to the power limit and the estimated de-queuing time is-larger than or equal to the predetermined threshold value.

4. The method according to claim 3 , wherein the deferring the transmitting the target command in the fourth case includes:

selecting at least one among tasks that do not require the memory device to consume power; and

performing the at least one selected task,

wherein the selecting selects at least one task based on de-queuing time of a command which is being de-queued from the memory command queue to the memory device.

5. The method according to claim 2 , further comprising updating the estimated power and the estimated de-queuing time.

6. The method according to claim 1 , wherein the target command is de-queued to the memory device when it is a turn to process the target command among a plurality of commands queued in the memory command queue.

7. The method according to claim 6 , further comprising providing a processing completion signal for the target command, to the controller from the memory device.

8. The method according to claim 7 , further comprising updating the estimated power and the estimated de-queuing time based on the processing completion signal.

9. The method according to claim 1 , wherein the estimated power consumption is an estimated amount of power required for the memory device to perform operations in response to all commands queued in the memory command queue, and

wherein the estimated de-queuing time is an estimated amount of time required for all the commands queued in the memory command queue to be de-queued.

10. A memory system comprising:

a controller configured to:

queue a plurality of commands input from an external device in a host command queue,

identify a target command among a plurality of commands queued in the host command queue,

control a transmission of the target command from the host command queue to a memory command queue based on an estimated power consumption of a memory device, and

control the transmission of the target command from the host command queue to the memory command queue based on an estimated de-queuing time of the memory command queue; and

the memory device, coupled to the controller via a channel, configured to:

receive the de-queued target command, and

perform an operation corresponding to the de-queued target command.

11. The memory system according to claim 10 , wherein the controller comprises:

a host interface configured to queue a plurality of commands provided from an exterior, in the host command queue;

a memory interface configured to queue a plurality of commands to be provided to the memory device, in the memory command queue;

a power manager configured to store the estimated power, the power limit and the estimated de-queuing time; and

a processor configured to:

identify the target command among the plurality of commands queued in the host command queue,

compare an estimated power of the memory device with a power limit,

transmit the target command from the host command queue to the memory command queue in response to the estimated power being smaller than the power limit, and

de-queue the target command from the memory command queue to the memory device.

12. The memory system according to claim 11 , wherein the processor in the first case transmits the target command from the host command queue to the memory command queue in response to the estimated power being larger than or equal to the power limit and the estimated de-queuing time smaller than a predetermined threshold value; and defers the transmitting the target command from the host command queue to the memory command queue in response to the estimated power being larger than or equal to the power limit and the estimated de-queuing time larger than or equal to the predetermined threshold value.

13. The memory system according to claim 12 , wherein the processor in the fourth case selects at least one among tasks that do not require the memory device to consume power, in the case where the estimated de-queuing time is larger than or equal to the predetermined threshold value, and performs the at least one selected task.

14. The memory system according to claim 13 , wherein the processor selects at least one task based on de-queuing time of a command which is being de-queued from the memory command queue to the memory device.

15. The memory system according to claim 12 , wherein the processor controls the power manager to update the estimated power and the estimated de-queuing time.

16. The memory system according to claim 11 , wherein the processor controls the memory interface to de-queue the target command to the memory device when it is a turn to process the target command among a plurality of commands queued in the memory command queue.

17. The memory system according to claim 16 , wherein the memory device provides a processing completion signal for the target command, to the controller.

18. The memory system according to claim 17 , wherein the power manager further updates the estimated power and the estimated de-queuing time based on the processing completion signal.

19. The memory system according to claim 11 , wherein the estimated power consumption is an estimated amount of power required for a memory device to perform operations in response to all commands queued in the memory command queue, and

wherein the estimated de-queuing time is an estimated amount of time required for all the commands queued in the memory command queue to be de-queued.

20. An operating method of a controller, the operating method comprising:

queuing a plurality of commands input from an external device in a host command queue;

controlling a transmission of the plurality of commands from the host command queue to a memory command queue based on an estimated power consumption of the memory device;

performing a task based on an estimated de-queuing time of the memory command queue; and

de-queueing the commands queued in the memory command queue to control a memory device to perform operations in response to the de-queued commands,

wherein the estimated power consumption is an estimated amount of power required for the memory device to perform the operations in response to all the commands currently queued in the memory command queue, and

wherein the estimated de-queuing time is an estimated amount of time required for all the commands queued in the memory command queue to be de-queued.