IP Library Granted Patent US 11,182,098
Granted Patent B2
US 11,182,098 · App. 16/588,585 · Granted Nov 23, 2021

Optimization for real-time, parallel execution of models for extracting high-value information from data streams

Inventors: Luis F. Stevens (San Jose, CA); Hrishikesh Vivek Prabhune (Columbus, IN); Pallav Agrawal (Edison, NJ); Vincent Schiavone (Berwyn, PA)
Assignee: Target Brands, Inc.
G06F3/0652G06F3/0604G06F3/0608G06F3/0631G06F3/0683G06F16/24568G06F16/9024G06K9/00G06Q50/01
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Quick Facts
Patent No.
US 11,182,098
App. No.
16/588,585
Granted
Nov 23, 2021
Kind
B2
Abstract

A computer system identifies high-value information in data streams. The computer system receives a filter graph definition. The filter graph definition includes a plurality of filter nodes, each filter node including one or more filters that accept or reject packets. Each respective filter is categorized by a number of operations, and the one or more filters are arranged in a general graph. The computer system performs one or more optimization operations, including: determining if a closed circuit exists within the graph, and when the closed circuit exists within the graph, removing the closed circuit; reordering the filters based at least in part on the number of operations; and parallelizing the general graph such that the one or more filters are configured to be executed on one or more processors.

Claims (33)

1. A method for accessing memory without using software-based locking techniques, the method comprising:

assigning an index number to each memory slot of a plurality of sequential memory slots of a shared non-circular memory array, wherein the index number assigned to each memory slot is based at least in part on a physical address of memory associated with that memory slot;

allocating a first memory slot and writing data to the first memory slot, wherein the first memory slot is associated with a producer index number;

reading data from a second memory slot, wherein the second memory slot is associated with a consumer index number; and

de-allocating data from a third memory slot having a second index number, wherein the third memory slot is associated with a garbage collector index number;

wherein the writing, reading and de-allocating are performed using atomic instructions.

2. The method of claim 1 , further comprising:

in accordance with a determination that a difference between the producer index number and the garbage collector index number does not exceed a maximum queue length threshold, writing data to a fourth memory slot, wherein the fourth memory slot is subsequent to the first memory slot in the sequential non-circular array.

3. The method of claim 2 , further comprising:

in accordance with a determination that a difference between the producer index number and the garbage collector index number exceeds a maximum queue length threshold, refraining from writing data to the fourth memory slot.

4. The method of claim 1 , further comprising:

in accordance with a determination that the consumer index number does not equal or exceed the producer index number, reading data from a fifth memory slot, wherein the fifth memory slot is subsequent to the second memory slot in the sequential non-circular array.

5. The method of claim 4 , further comprising:

in accordance with a determination that the consumer index number does equal the producer index number, refraining from reading data from the fifth memory slot.

6. The method of claim 1 , further comprising:

in accordance with a determination that the garbage collector index number does not meet or exceed the consumer index number, de-allocating data from a sixth memory slot, wherein the sixth memory slot is subsequent to the third memory slot in the sequential non-circular array.

7. The method of claim 6 , further comprising:

in accordance with a determination that the garbage collector index number does not meet or exceed the consumer index number, refraining from de-allocating data from the sixth memory slot.

8. The method of claim 1 , wherein the allocating includes:

retrieving a bitmap portion from a bitmap, wherein the bitmap identifies whether a state record for a queue thread state is allocated;

determining, using a single atomic instruction, whether the bitmap portion includes a bit that indicates that a memory block is available for allocation;

if the bitmap portion includes a bit that indicates that a memory block is available for allocation, performing a series of atomic instructions, per bit, to identify the bit that indicates that the memory block is available for allocation;

after identifying the bit, allocating the memory block to correspond to the first memory slot in the memory array; and

de-allocating the memory block by identifying a global position in the bitmap of the bitmap portion and subsequently identifying a bit position in the identified bitmap portion that corresponds to the previously-identified memory block.

9. The method of claim 8 , wherein the bitmap portion comprises a word.

10. A computing system including a processor and a memory, the memory storing a shared non-circular memory array and instructions which, when executed by the processor, cause the computing system to:

assign an index number to each memory slot of a plurality of sequential memory slots of a shared non-circular memory array, wherein the index number assigned to each memory slot is based at least in part on a physical address of memory associated with that memory slot;

allocate a first memory slot and writing data to the first memory slot, wherein the first memory slot is associated with a producer index number;

read data from a second memory slot, wherein the second memory slot is associated with a consumer index number; and

de-allocate data from a third memory slot having a second index number, wherein the third memory slot is associated with a garbage collector index number;

wherein the writing, reading and de-allocating are performed using atomic instructions.

11. The computing system of claim 10 , wherein the memory comprises a plurality of memory devices and the processor comprises a plurality of processors, and the shared non-circular memory array is stored on at least one of the plurality of memory devices.

12. The computing system of claim 10 , wherein the instructions include a producer process, a consumer process, and a garbage collector process.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 5, 2021
From: UDA, LLC; AKUDA LABS, LLC
To: TARGET BRANDS, INC.
Reel/Frame 055166/0843 →
Continuity (12)
Continuation 15360934 · Nov 23, 2016
Continuation In Part 14214490 · Mar 14, 2014
Continuation In Part 14688865 · Apr 16, 2015
Continuation In Part 14214410 · Mar 14, 2014
Provisional Application 62259021 · Nov 23, 2015
Provisional Application 62259023 · Nov 23, 2015
Provisional Application 62259024 · Nov 23, 2015
Provisional Application 62259026 · Nov 23, 2016
Provisional Application 62264845 · Dec 8, 2015
Provisional Application 61802353 · Mar 15, 2013
Provisional Application 61980525 · Apr 16, 2014
Related Publication 20200026456A1 · Jan 23, 2020
Cited By (4)
US 12,248,361 US 12,436,778 US 12,561,349 US 12,625,885