SYSTEMS AND METHODS FOR PROVIDING REAL-TIME PRE-TRADE RISK ASSESSMENT
Systems and methods are disclosed that provide real-time pre-trade risk assessments for multiple parties. In one embodiment, a Programmable Logic Device (PLD) may be embedded within an Automated Trading Systems (ATS) architecture by utilizing the Intel socket G or the PCIe interface to provide pre-trade risk functionality. The system may also provide a method for interacting with the ATS DRAM or L1 cache to provide faster access to orders in ATS memory for PLDs. The system may use the Quick Path Interconnect between an embedded processor and a PLD to transfer memory maps. The system may also add additional libraries to an ATS processor to accelerate the transfer or memory maps to a PLD. The system also may use system interrupts to cancel erroneous orders within an ATS processor from a PLD housed within the same physical architecture.
1 . A system comprising:
a first memory;
a shadow map of the first memory;
an automated trading system (ATS) processor in communication with the first memory and the shadow map, the ATS processor configured to
receive market data information,
write market order information to the first memory based on the market data information,
update the shadow map based on the market order information written to the first memory, and
prepare a market order for transmission to a market venue based on the market order information; and
a trade risk processor in communication with the ATS processor, the trade risk processor configured to
obtain the market order information from the shadow map, and
perform a trade risk assessment based on the market order information obtained from the shadow map, wherein
performance of the trade risk assessment and preparation of the market order are simultaneous.
2 . The system of claim 1 , wherein the trade risk processor is in communication with the ATS processor via a PCIe connection.
3 . The system of claim 2 , wherein the first memory comprises a dynamic random access memory.
4 . The system of claim 3 , wherein the ATS processor is further configured to write the market order information to a predictable location on the dynamic random access memory.
5 . The system of claim 1 , wherein the trade risk processor is in communication with the ATS processor via an Intel Socket G connection.
6 . The system of claim 5 , wherein the first memory comprises a cache memory.
7 . The system of claim 6 , wherein the ATS processor is further configured to write the market order information to a predictable location on the cache memory.
8 . The system of claim 7 , wherein the ATS processor is further configured to copy the market order information from the cache memory to the shadow map via a Quick Path Interconnect.
9 . The system of claim 1 , wherein the trade risk processor is further configured to:
determine whether the market order information satisfies one or more risk criteria, and
if it is determined that the market order information does not satisfy the risk criteria, transmit a cancel order command to the ATS processor.
10 . The system of claim 9 , wherein the cancel order command is transmitted to the ATS processor before the ATS processor completes preparing the market order for transmission to a market venue.
11 . The system of claim 9 , wherein the cancel order command is transmitted via a system interrupt.
12 . The system of claim 11 , wherein the system interrupt is transmitted to the ATS processor via a Northbridge associated with the ATS processor.
13 . A system comprising:
a first cache memory;
a shadow map of the first cache memory;
an automated trading system (ATS) processor in communication with the first cache memory and the shadow map, the ATS processor configured to
receive market data information,
write market order information to the first cache memory based on the market data information,
update the shadow map based on the market order information written to the first cache memory, and
prepare a market order for transmission to a market venue based on the market order information; and
a trade risk processor in communication with the ATS processor, the trade risk processor configured to
obtain the market order information from the shadow map, and
perform a trade risk assessment based on the market order information obtained from the shadow map, wherein
performance of the trade risk assessment and preparation of the market order are simultaneous.
14 . The system of claim 13 , wherein the trade risk processor is in communication with the ATS processor via an Intel Socket G connection.
15 . The system of claim 14 , wherein the ATS processor is further configured to copy the market order information from the first cache memory to the shadow map.
16 . The system of claim 15 , wherein the market order information is copied from the first cache memory to the shadow map via a Quick Path Interconnect.
17 . A computer-implemented method comprising:
receiving, by a computing system, market data information;
storing, by the computing system, market order information in a first memory based on the market data information;
preparing, by the computing system, a market order for transmission to a market venue based on the market order information;
updating, by the computing system, a shadow map based on the storing the market order information in the first memory; and
performing, by the computing system, a trade risk assessment based on the updated shadow map, wherein
the preparing the market order and the performing the trade risk assessment are simultaneous.
18 . The computer-implemented method of claim 17 further comprising:
determining that the market order information does not satisfy trade risk criteria, and
transmitting a cancel order command to an automated trading system (ATS) processor of the computing system.
19 . The computer-implemented method of claim 18 , wherein the cancel order command is transmitted to the ATS processor before the preparing the market order for transmission to a market venue has completed.
20 . The computer-implemented method of claim 18 , wherein the cancel order command is transmitted via a system interrupt.