IP Library Granted Patent US 11,068,292
Granted Patent B2
US 11,068,292 · App. 16/589,100 · Granted Jul 20, 2021

Computing system translation to promote efficiency

Inventor: Kristy-Leigh Anne Minehan (Bellevue, WA)
G06F9/4552G06F9/30083G06F9/44505G06F9/4893G06F9/524G06Q20/0658G06Q20/3678G06Q20/381
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 11,068,292
App. No.
16/589,100
Granted
Jul 20, 2021
Kind
B2
Abstract

A system and method for utilizing the processing power of computing devices such as smart devices are provided. The system includes one or more distributed smart devices and a management server that communicates with the smart devices in order to determine whether they are idle and whether viable compute tasks are present that can be performed on the smart devices based on the smart device's status, configuration, utility and network parameters, and availability. Some tasks may be performed in low power mode to save energy.

Claims (31)

1. A computing system, comprising:

a first computing device; and

a second computing device, including:

a processor; and

a compiler;

wherein the first computing device is configured to obtain a profile of the processor of the second computing device, select an algorithm from a plurality of algorithms for the processor of the second computing device to compute while the second computing device is in an idle power mode, and provide instructions for computing the selected algorithm from the plurality of algorithms;

wherein the selected algorithm from the plurality of algorithms corresponds to a maximum expected efficiency value of the plurality of algorithms;

wherein the first computing device is further configured to test the plurality of algorithms for the second computing device prior to selecting the algorithm from the plurality of algorithms; and

wherein the compiler of the second computing device is configured to automatically convert the provided instructions to a different language that is compatible with the processor of the second computing device.

2. The computing system of claim 1 , wherein the profile of the processor of the second computing device includes a model or part number, a voltage, a clock speed, and/or an expected instruction language.

3. The computing system of claim 1 , wherein the first computing device is further configured to obtain an idle power consumption of the second computing device.

4. The computing system of claim 3 , wherein the selected algorithm from the plurality of algorithms corresponds to an expected power consumption that is less than or equal to the idle power consumption of the second computing device.

5. The computing system of claim 3 , wherein the selected algorithm from the plurality of algorithms corresponds to a maximum expected value of the plurality of algorithms with an expected power consumption that is less than or equal to the idle power consumption of the second computing device.

6. The computing system of claim 1 , wherein the first computing device is further configured to store results of the testing of the plurality of algorithms for the second computing device for use in selecting algorithms for other second computing devices.

7. A method of operating a computing system having a plurality of computing devices, the method comprising:

using a first computing device to obtain a profile of a processor of a second computing device;

selecting, via the first computing device, a list of algorithms, from a plurality of algorithms, for the second computing device;

testing operations of the second computing device with algorithms of the list of algorithms;

storing results from the testing of the operations of the second computing device in a storage device connected to the first computing device;

determining a most efficient algorithm from the list of algorithms, wherein the most efficient algorithm is an algorithm with a highest expected efficiency value;

providing instructions from the first computing device to the second computing device for computing the most efficient algorithm;

translating, via a compiler of the second computing device, the instructions from a first language to a second language;

providing the translated instructions in the second language to the processor of the second computing device; and

operating the second computing device according to the translated instructions to compute the most efficient algorithm.

8. The method of claim 7 , wherein the profile of the processor of the second computing device includes a part number of the processor of the second computing device, a voltage of the processor of the second computing device, a clock speed of the processor of the second computing device, and an indication of the second language.

9. The method of claim 7 , including determining when the second computing device is operating in a low power mode; wherein operating the second computing device according to the translated instructions includes operating the second computing device according to the translated instructions only when the second computing device is in the low power mode.

10. The method of claim 9 , wherein operating the second computing device according to the translated instructions includes operating the second computing device without substantially increasing power consumption of the second computing device.

11. The method of claim 7 , including obtaining a low power consumption of the second computing device; wherein operating the second computing device according to the translated instructions includes operating the second computing device with a power consumption at or below the low power consumption of the second computing device.

12. The method of claim 11 , wherein the most efficient algorithm does not cause the second computing device to consume more power than the low power consumption of the second computing device.

13. The method of claim 7 , including automatically converting cryptocurrency rewards for computing the most efficient algorithm into a fiat currency and crediting an account associated with an owner of the second computing device with the fiat currency.

14. The method of claim 7 , wherein testing the operations of the second computing device with the algorithms of the list of algorithms includes simulating performance of the second computing device.

Assignments (20)
RELEASE OF SECURITY INTEREST Recorded May 6, 2026
From: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
To: CORE SCIENTIFIC, INC.
Reel/Frame 075520/0577 →
SECURITY INTEREST Recorded Mar 10, 2026
From: CORE SCIENTIFIC, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
Reel/Frame 075099/0814 →
RELEASE OF SECURITY INTEREST Recorded Sep 13, 2024
From: WILMINGTON TRUST, NATIONAL ASSOCIATION
To: CORE SCIENTIFIC, INC.
Reel/Frame 068968/0373 →
RELEASE OF SECURITY INTEREST Recorded Aug 28, 2024
From: B. RILEY COMMERCIAL CAPITAL, LLC
To: CORE SCIENTIFIC, INC.; CORE SCIENTIFIC OPERATING COMPANY
Reel/Frame 068803/0146 →
RELEASE OF SECURITY INTEREST Recorded Aug 20, 2024
From: WILMINGTON TRUST, NATIONAL ASSOCIATION
To: CORE SCIENTIFIC, INC.
Reel/Frame 068693/0052 →
RELEASE OF SECURITY INTEREST Recorded Aug 20, 2024
From: WILMINGTON TRUST, NATIONAL ASSOCIATION
To: CORE SCIENTIFIC, INC.
Reel/Frame 068719/0600 →
SECURITY INTEREST Recorded Jul 29, 2024
From: CORE SCIENTIFIC, INC.
To: WILMINGTON TRUST, NATIONAL ASSOCIATION
Reel/Frame 068178/0677 →
SECURITY INTEREST Recorded Jul 29, 2024
From: CORE SCIENTIFIC, INC.
To: WILMINGTON TRUST, NATIONAL ASSOCIATION
Reel/Frame 068178/0585 →
SECURITY INTEREST Recorded Jul 29, 2024
From: CORE SCIENTIFIC, INC.
To: WILMINGTON TRUST, NATIONAL ASSOCIATION
Reel/Frame 068178/0700 →
MERGER Recorded Feb 6, 2024
From: CORE SCIENTIFIC OPERATING COMPANY
To: CORE SCIENTIFIC, INC.
Reel/Frame 066507/0675 →
RELEASE OF SECURITY INTEREST Recorded Jan 26, 2024
From: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
To: CORE SCIENTIFIC OPERATING COMPANY; CORE SCIENTIFIC ACQUIRED MINING LLC
Reel/Frame 066375/0324 →
RELEASE OF SECURITY INTEREST Recorded Jan 26, 2024
From: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
To: CORE SCIENTIFIC, INC.
Reel/Frame 066375/0365 →
SECURITY INTEREST Recorded Mar 1, 2023
From: CORE SCIENTIFIC, INC.; CORE SCIENTIFIC OPERATING COMPANY
To: B. RILEY COMMERCIAL CAPITAL, LLC
Reel/Frame 062899/0741 →
RELEASE OF SECURITY INTEREST Recorded Feb 3, 2023
From: WILMINGTON SAVINGS FUND SOCIETY, FSB
To: CORE SCIENTIFIC INC.; CORE SCIENTIFIC OPERATING COMPANY
Reel/Frame 063272/0450 →
SECURITY INTEREST Recorded Dec 23, 2022
From: CORE SCIENTIFIC OPERATING COMPANY; CORE SCIENTIFIC INC.
To: WILMINGTON SAVINGS FUND SOCIETY, FSB
Reel/Frame 062218/0713 →
SECURITY INTEREST Recorded Feb 10, 2022
From: CORE SCIENTIFIC OPERATING COMPANY; CORE SCIENTIFIC ACQUIRED MINING LLC
To: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 059004/0831 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 18, 2021
From: MINEHAN, KRISTY-LEIGH ANNE
To: CORE SCIENTIFIC, INC.
Reel/Frame 056581/0261 →
SECURITY INTEREST Recorded Apr 21, 2021
From: CORE SCIENTIFIC, INC.
To: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 055996/0839 →
RELEASE OF SECURITY INTEREST Recorded Apr 21, 2021
From: SILVERPEAK CREDIT PARTNERS LP
To: CORE SCIENTIFIC, INC.
Reel/Frame 055990/0111 →
SECURITY INTEREST Recorded May 21, 2020
From: CORE SCIENTIFIC, INC.
To: SILVERPEAK CREDIT PARTNERS LP
Reel/Frame 052722/0349 →
Continuity (3)
Continuation 16587860 · Sep 30, 2019
Provisional Application 62892029 · Aug 27, 2019
Related Publication 20210064399A1 · Mar 4, 2021