Method and system for in-line ECC protection
A memory system having an interconnect configured to receive commands from a system to read data from and/or write data to a memory device. The memory system also has a bridge configured to receive the commands from the interconnect, to manage ECC data and to perform address translation between system addresses and physical memory device addresses by calculating a first ECC memory address for a first ECC data block that is after and adjacent to a first data block having a first data address, calculating a second ECC memory address that is after and adjacent to the first ECC block, and calculating a second data address that is after and adjacent to the second ECC block. The bridge may also check and calculate ECC data for a complete burst of data, and/or cache ECC data for a complete burst of data that includes read and/or write data.
1. An integrated circuit comprising:
an interconnect configured to receive, from a system, commands to read data from and/or write data to physical addresses of a memory device; and
a bridge configured to receive the commands from the interconnect and to perform address translation between system addresses and the physical addresses by:
calculating a first ECC memory address for a first ECC data block that is after and adjacent to a first address of a first data block;
calculating a second ECC memory address for a second ECC data block that is after and adjacent to the first ECC memory address of the first ECC data block; and
calculating a second data address for a second data block that is after and adjacent to the second ECC memory address of the second ECC data block.
2. The integrated circuit of claim 1 , wherein the first ECC data block contains ECC data for the first data block and the second ECC data block contains ECC data for the second data block.
3. The integrated circuit of claim 1 , wherein the first ECC data block and the second ECC data block are each 64 bytes and the first data block and the second data block are each 512 bytes.
4. The integrated circuit of claim 1 , wherein the first data address, the second data address, the first ECC memory address, and the second ECC memory address correspond to contiguous locations in the memory device.
5. The integrated circuit of claim 1 further comprising a set of processors coupled to the interconnect and configured to provide the commands to the interconnect.
6. The integrated circuit of claim 5 further comprising a memory and a memory controller coupled between the memory and the bridge.
7. The integrated circuit of claim 1 , wherein the bridge is configured to:
calculate the first ECC data block based on the first data block; and
calculate the second ECC data block based on the second data block.
8. The integrated circuit of claim 1 , wherein the bridge is configured to perform the address translation such that:
the first address of the first data block and the second address of the second data block are powers of two; and
the first ECC memory address and the second ECC memory address are not powers of two.
9. A memory system comprising:
a memory device;
a processor;
an interconnect configured to receive, from the processor, commands to read data from and/or write data to physical addresses of the memory device; and
a bridge configured to receive the commands from the interconnect and to perform address translation between system addresses and the physical addresses by:
calculating a first ECC memory address for a first ECC data block that is after and adjacent to a first address of a first data block;
calculating a second ECC memory address for a second ECC data block that is after and adjacent to the first ECC memory address of the first ECC data block; and
calculating a second data address for a second data block that is after and adjacent to the second ECC memory address of the second ECC data block.
10. The memory system of claim 9 , wherein the first ECC data block contains ECC data for the first data block and the second ECC data block contains ECC data for the second data block.
11. The memory system of claim 9 , wherein the first ECC data block and the second ECC data block are each 64 bytes and the first data block and the second data block are each 512 bytes.
12. The memory system of claim 9 , wherein the first data address, the second data address, the first ECC memory address, and the second ECC memory address correspond to contiguous locations in the memory device.
13. A method of translating system memory addresses to physical memory addresses, the method comprising:
providing a first ECC block associated with a first data block;
providing a second ECC block associated with a second data block;
calculating a first ECC memory address for the first ECC data block that is after and adjacent to a first data address of the first data block;
calculating a second ECC memory address that is after and adjacent to the first ECC memory address of the first ECC block; and
calculating a second data address for the second data block that is after and adjacent to the second ECC memory address of the second ECC block.
14. The method of claim 13 , wherein the first data block, the first ECC block, the second ECC block, and the second data block are contiguous in memory based on the first data address, the first ECC memory address, the second ECC memory address, and the second data address.
15. A bridge device comprising:
a command arbiter configured to couple between a set of processors and a memory and configured to receive an instruction to write, to the memory, a set of data that includes a first data block and a second data block;
an error correcting code (ECC) circuit coupled to the command arbiter and configured to, based on the instruction:
generate a first ECC block based on the first data block;
generate a second ECC block based on the second data block;
generate a set of addresses for the first data block, the first ECC block, the second data block, and the second ECC block such that the first ECC block is to be stored in the memory adjacent to the second ECC block; and
provide the first data block, the first ECC block, the second data block, and the second ECC block for storing in the memory.
16. The bridge device of claim 15 , wherein ECC circuit is configured to generate the set of addresses such that the first data block, the first ECC block, the second data block, and the second ECC block are to be stored in the memory contiguously.
17. The bridge device of claim 15 , wherein ECC circuit is configured to generate the set of addresses such that the first ECC block and the second ECC block are to be stored in the memory between the first data block and the second data block.
18. The bridge device of claim 15 , wherein ECC circuit is configured to generate the set of addresses such that:
a first address of the first data block and a second address of the second data block are powers of two; and
a third address of the first ECC block and a fourth address of the second ECC block are not powers of two.
19. The bridge device of claim 15 , wherein:
the instruction includes a first subset of the set of data; and
the bridge device includes a read-modify-write block coupled between the command arbiter and the error correcting code and configured to, based on the instruction including a read modify-write instruction:
read a second subset of the set of data from the memory;
merge the first subset and the second subset to produce the set of data; and
provide the set of data to the ECC circuit.
20. The bridge device of claim 15 , wherein the bridge device is configured to couple to the memory via a memory controller.