Devices and electronic systems including vertical transistors, and related methods
A device comprises vertically oriented transistors. The device comprises a pillar comprising at least one oxide semiconductor material, the pillar wider in a first lateral direction at an upper portion thereof than at a lower portion thereof, a gate dielectric material over sidewalls of the pillar and extending in the first lateral direction, and at least one gate electrode adjacent to at least a portion of the gate dielectric material. Related devices, electronic systems, and methods are also disclosed.
1. A device, comprising:
at least one pillar comprising a composite oxide semiconductor material, the at least one pillar wider in a first lateral direction at an upper portion thereof than at a lower portion thereof, the composite oxide semiconductor material comprising:
a first oxide semiconductor material; and
a second oxide semiconductor material between portions of the first oxide semiconductor material and comprising a different material composition than the first oxide semiconductor material;
a gate dielectric material adjacent to sidewalls of the at least one pillar and extending in the first lateral direction; and
at least one gate electrode adjacent to at least a portion of the gate dielectric material.
2. The device of claim 1 , wherein the at least one pillar is wider in a second, different lateral direction at the lower portion thereof than at the upper portion thereof.
3. The device of claim 1 , wherein the composite oxide semiconductor material comprises one or more of zinc tin oxide, indium zinc oxide, zinc oxide, indium gallium zinc oxide, indium gallium silicon oxide, indium oxide, tin oxide, titanium oxide, zinc oxide nitride, magnesium zinc oxide, indium zinc oxide, zirconium indium zinc oxide, hafnium indium zinc oxide, tin indium zinc oxide, aluminum tin indium zinc oxide, silicon indium zinc oxide, zinc tin oxide, aluminum zinc tin oxide, gallium zinc tin oxide, zirconium zinc tin oxide, indium gallium silicon oxide, and indium tungsten oxide.
4. The device of claim 1 , wherein the composite oxide semiconductor material comprises indium gallium zinc oxide.
5. The device of claim 1 , wherein the composite oxide semiconductor material comprises an unetched material.
6. The device of claim 1 , wherein the first oxide semiconductor material comprises indium gallium silicon oxide.
7. The device of claim 1 , wherein the at least one gate electrode comprises two gate electrodes over two opposing surfaces of the at least one pillar.
8. A method of forming a device, comprising:
forming first trenches in an electrically insulative material;
forming a sacrificial material within the first trenches;
forming second trenches in the electrically insulative material and the sacrificial material;
forming a gate dielectric material within the second trenches;
forming a gate electrode material adjacent to at least a portion of the gate dielectric material;
filling remaining portions of the second trenches with an electrically insulative material;
removing remaining portions of the sacrificial material to form openings; and
forming a composite oxide semiconductor material within the openings, the composite oxide semiconductor material comprising a second oxide semiconductor material between portions of a first oxide semiconductor material, the second oxide semiconductor material comprising a different material composition than the first oxide semiconductor material, forming the composite oxide semiconductor material comprising:
forming at least one pillar comprising the composite oxide semiconductor material, the at least one pillar wider in a first lateral direction at an upper portion thereof than at a lower portion thereof.
9. The method of claim 8 , wherein forming a sacrificial material within the first trenches comprises filling the first trenches with carbon.
10. The method of claim 8 , wherein forming a sacrificial material within the first trenches comprises filling the first trenches with polysilicon.
11. The method of claim 8 , wherein forming a composite oxide semiconductor material within the openings comprises forming indium gallium zinc oxide within the openings.
12. The method of claim 8 , wherein forming a composite oxide semiconductor material within the openings comprises forming one or more of zinc tin oxide, indium zinc oxide, zinc oxide, indium gallium zinc oxide, indium gallium silicon oxide, indium oxide, tin oxide, titanium oxide, zinc oxide nitride, magnesium zinc oxide, indium zinc oxide, zirconium indium zinc oxide, hafnium indium zinc oxide, tin indium zinc oxide, aluminum tin indium zinc oxide, silicon indium zinc oxide, zinc tin oxide, aluminum zinc tin oxide, gallium zinc tin oxide, zirconium zinc tin oxide, indium gallium silicon oxide, and indium tungsten oxide within the openings.
13. The method of claim 8 , wherein forming a composite oxide semiconductor material comprises forming the composite oxide semiconductor material through atomic layer deposition.
14. The method of claim 8 , wherein forming openings comprises forming upper portions of the openings to be wider in the first lateral direction than in a second, different lateral direction.
15. The method of claim 8 , wherein forming a composite oxide semiconductor material comprises forming the at least one pillar comprising the composite oxide semiconductor material without etching the composite oxide semiconductor material.
16. A method of forming a device, comprising:
forming pillars over a conductive line, each of the pillars comprising a sacrificial material vertically extending orthogonal to the conductive line;
forming a gate dielectric material adjacent to sidewalls of the pillars;
forming a gate electrode material adjacent to the gate dielectric material;
removing the sacrificial material to form openings; and
forming an oxide semiconductor material within the openings to form vertically oriented pillars over the conductive line, the vertically oriented pillars comprising an unetched oxide semiconductor material, forming the oxide semiconductor material comprising:
forming a first oxide semiconductor material within the openings; and
forming a second oxide semiconductor material between portions of the first oxide semiconductor material and comprising a different material composition than the first oxide semiconductor material.
17. The method of claim 16 , wherein forming an oxide semiconductor material within the openings comprises forming indium gallium zinc oxide within at least a portion of the openings.
18. The method of claim 16 , wherein forming an oxide semiconductor material within the openings comprises:
forming the first oxide semiconductor material comprising indium gallium silicon oxide within the openings; and
forming indium gallium zinc oxide between portions of the indium gallium silicon oxide within the openings.
19. The method of claim 16 , wherein forming an oxide semiconductor material within the openings comprises filling the openings with one or more of zinc tin oxide, indium zinc oxide, zinc oxide, indium gallium zinc oxide, indium gallium silicon oxide, indium oxide, tin oxide, titanium oxide, zinc oxide nitride, magnesium zinc oxide, indium zinc oxide, zirconium indium zinc oxide, hafnium indium zinc oxide, tin indium zinc oxide, aluminum tin indium zinc oxide, silicon indium zinc oxide, zinc tin oxide, aluminum zinc tin oxide, gallium zinc tin oxide, zirconium zinc tin oxide, indium gallium silicon oxide, and indium tungsten oxide.
20. The method of claim 16 , wherein forming pillars over a conductive line comprises forming polysilicon pillars or carbon pillars over the conductive line.
21. The method of claim 16 , wherein forming an oxide semiconductor material comprises forming the oxide semiconductor material by atomic layer deposition.
22. The method of claim 16 , further comprising recessing a portion of the oxide semiconductor material to form recessed portions, and forming another conductive line over the oxide semiconductor material in the recessed portions.
23. The method of claim 22 , further comprising performing chemical mechanical planarization on the device after forming the another conductive line over the oxide semiconductor material.
24. The method of claim 16 , wherein forming a gate electrode material over the gate dielectric material comprises forming the gate electrode material over two opposing side surfaces of each of the pillars.
25. A device, comprising:
a vertically oriented pillar over a conductive line, the vertically oriented pillar comprising an unetched oxide semiconductor material comprising:
a first oxide semiconductor material; and
a second oxide semiconductor material between portions of the first oxide semiconductor material and comprising a different material composition than the first oxide semiconductor material;
a gate dielectric material adjacent to the vertically oriented pillar;
at least one gate electrode adjacent to the gate dielectric material; and
a conductive contact over the vertically oriented pillar.
26. The device of claim 25 , wherein the unetched oxide semiconductor material exhibits at least one opening therein.
27. The device of claim 25 , wherein the unetched oxide semiconductor material is continuous and substantially free of openings therein.
28. The device of claim 25 , wherein the at least one gate electrode comprises two gate electrodes over two opposing side surfaces of the vertically oriented pillar.
29. The device of claim 25 , wherein the at least one gate electrode comprises a single gate electrode surrounding around all side surfaces of the vertically oriented pillar.
30. An electronic system, comprising:
at least one input device;
at least one output device;
at least one processor device operably coupled to the at least one input device and the at least one output device; and
a device operably coupled to the at least one processor device, the device comprising:
pillars each comprising at least one oxide semiconductor material, the pillars wider at an upper portion of the pillars than at a lower portion of the pillars in a first lateral direction and wider at the lower portion than at the upper portion in a second lateral direction;
a gate dielectric material adjacent to sidewalls of each pillar, the gate dielectric material extending in a direction of the wider upper portion thereof; and
at least one gate electrode adjacent to at least a portion of the gate dielectric material.
31. A method of forming a device, the method comprising:
forming a gate dielectric material adjacent to a sacrificial material;
forming at least one gate electrode adjacent to the gate dielectric material;
removing the sacrificial material to form an opening; and
forming a composite oxide semiconductor material in the opening, forming the composite oxide semiconductor material comprising:
forming a first oxide semiconductor material within at least a portion of the opening; and
forming a second oxide semiconductor material comprising a different material composition than the first oxide semiconductor material between portions of the first oxide semiconductor material within the opening to form at least one pillar comprising the composite oxide semiconductor material, the at least one pillar wider in a first lateral direction at an upper portion thereof than at a lower portion thereof,
the gate dielectric material adjacent to sidewalls of the at least one pillar and extending in the first lateral direction and the at least one gate electrode adjacent to at least a portion of the gate dielectric material.
32. The method of claim 31 , wherein forming a first oxide semiconductor material comprises forming the first oxide semiconductor material by atomic layer deposition.
33. The method of claim 31 , wherein forming a second oxide semiconductor material comprises forming the second oxide semiconductor material comprising the same elements and a different stoichiometry than the first oxide semiconductor material.