Methods for row hammer mitigation and memory devices and systems employing the same
Memory devices and methods of operating memory devices in which refresh management operations can be scheduled on an as-needed basis for those memory portions where activity (e.g., activations in excess of a predetermined threshold) warrants a refresh management operation are disclosed. In one embodiment, an apparatus comprises a memory including a memory location, and circuitry configured to determine a count corresponding to a number of activations at the memory location, to schedule a refresh management operation for the memory location in response to the count exceeding a first predetermined threshold, and to decrease the count by an amount corresponding to the first predetermined threshold in response to executing the scheduled refresh management operation. The circuitry may be further configured to disallow, in response to determining that the count has reached a maximum permitted value, further activations at the memory location until after the count has been decreased.
1. A method, comprising:
determining a count corresponding to a number of activations at a memory location of a memory device;
scheduling a refresh management operation for the memory location in response to the count exceeding a first predetermined threshold; and
decreasing the count by an amount corresponding to the first predetermined threshold in response to executing the scheduled refresh management operation,
wherein the amount is less than the count.
2. The method of claim 1 , wherein the refresh management operation is a first refresh management operation, the method further comprising:
scheduling, before the execution of the first refresh management operation, a second refresh management operation in response to the count exceeding the first predetermined threshold; and
decreasing the count by the amount corresponding to the first predetermined threshold in response to executing the second scheduled refresh management operation.
3. The method of claim 2 , further comprising:
disallowing, in response to determining that the count has reached a maximum permitted value, further activations at the memory location until after the count has been decreased.
4. The method of claim 1 , wherein the memory location comprises a memory bank.
5. The method of claim 4 , wherein the refresh management operation comprises refreshing a subset of a plurality of rows of the memory bank impacted by the activations.
6. The method of claim 1 , wherein the amount is a first amount, and further comprising:
decreasing the count by a second amount in response to executing a periodic refresh operation at the memory location.
7. The method of claim 6 , wherein the periodic refresh operation comprises refreshing only a single memory bank including the memory location.
8. The method of claim 6 , wherein the periodic refresh operation comprises refreshing a plurality of memory banks of the memory device.
9. The method of claim 1 , wherein the memory location comprises a subset of a plurality of rows of the memory device.
10. An apparatus, comprising:
a memory including a memory location; and
circuitry configured to:
determine a count corresponding to a number of activations at the memory location;
schedule a refresh management operation for the memory location in response to the count exceeding a first predetermined threshold; and
decrease the count by an amount corresponding to the first predetermined threshold in response to executing the scheduled refresh management operation,
wherein the amount is less than the count.
11. The apparatus of claim 10 , wherein the refresh management operation is a first refresh management operation, and wherein the circuitry is further configured to:
schedule, before the execution of the first refresh management operation, a second refresh management operation in response to the count exceeding the first predetermined threshold; and
decrease the count by the amount corresponding to the first predetermined threshold in response to executing the second scheduled refresh management operation.
12. The apparatus of claim 11 , wherein the circuitry is further configured to:
disallow, in response to determining that the count has reached a maximum permitted value, further activations at the memory location until after the count has been decreased.
13. The apparatus of claim 10 , wherein the memory location comprises a memory bank.
14. The apparatus of claim 13 , wherein the refresh management operation comprises refreshing a subset of a plurality of rows of the memory bank impacted by the activations.
15. The apparatus of claim 10 , wherein the amount is a first amount, and wherein the circuitry is further configured to:
decrease the count by a second amount in response to executing a periodic refresh operation at the memory location.
16. The apparatus of claim 15 , wherein the periodic refresh operation comprises refreshing only a single memory bank including the memory location.
17. The apparatus of claim 15 , wherein the periodic refresh operation comprises refreshing a plurality of memory banks of the memory device.
18. The apparatus of claim 10 , wherein the memory comprises a dynamic random access memory (DRAM) device.
19. An apparatus, comprising:
a memory including a memory location; and
circuitry configured to:
determine a count corresponding to a number of activations at the memory location;
disallow, in response to determining that the count has reached a maximum permitted value, further activations at the memory location until after the count has been decreased; and
decrease the count by a predetermined amount in response to receiving a command to execute a refresh management operation at the memory location, wherein the amount is less than the count.
20. The apparatus of claim 19 , wherein the memory location is a memory bank, and wherein the refresh management operation comprises refreshing a subset of a plurality of rows of the memory bank impacted by the activations.
21. The apparatus of claim 19 , wherein the memory comprises a dynamic random access memory (DRAM) device.