Method and apparatus for selectable high performance or low power processor system
A communications processor is operative in a plurality of modes including at least a high performance mode, a power savings mode with lower computational capability, and a shutdown mode with a wakeup capability. A memory for the communications processor has a high speed segment and a low speed segment, the high speed segment and low speed segment respectively on a high speed data bus and a low speed data bus, the high speed data bus and low speed data bus coupled by a bidirectional bridge.
1. A processor operative for incremental operation from a power savings mode to a high performance mode, the processor comprising:
a central processing unit (CPU);
a performance register having a plurality of states, each state associated with a particular level of performance and power consumption;
a processor clock source having an output coupled to the CPU and having a frequency controlled by the performance register;
a voltage source coupled to the CPU, the voltage source controlled by the performance register, each voltage coupled to the CPU also associated with a minimum voltage required to ensure operation of the CPU at each particular clock frequency selected by the performance register;
a high speed bus coupled to the CPU, a high speed RAM, and also to a low power RAM;
a low power bus coupled to the CPU and also coupled to the performance register, the low power bus also coupled to a packet energy detector periodically sampling an RF energy level and storing the samples in a low power static random access memory (LPSRAM);
a bridge coupling between the high speed bus and low power bus;
the processor clock source comprising at least one of a ring oscillator or resistor/capacitor (RC) oscillator enabled for a low power state and a PLL enabled for a high performance state;
the CPU periodically waking up from a power savings mode to examine the stored samples and changing the performance register to a higher performance state when an increase in RF energy level is detected.
2. The processor of claim 1 where said performance register has a PS0 value for a sleep state, a PS1 value for a standby state, a PS2 value for a low power operational state, a PS3 value for a medium performance state, and a PS4 value for a high performance state.
3. The processor of claim 1 where said low speed bus is a Serial Peripheral Interface (SPI) bus.
4. The processor of claim 2 where said PS2 value is associated with a CPU voltage of approximately 0.7V and a clock rate of approximately 32 Mhz.
5. The processor of claim 2 where said PS3 value is associated with a CPU voltage of approximately 0.9V and a clock rate of approximately 100 Mhz.
6. The processor of claim 2 where said PS4 value is associated with a CPU voltage of approximately 1.1V and a clock rate of approximately 180 Mhz.
7. The processor of claim 1 where said voltage source is a linear regulator enabled for a low power state and a switching regulator enabled for a high performance state.
8. The processor of claim 1 where said high speed bus includes an address bus and an associated data bus.
9. A processor comprising:
a central processing unit (CPU);
a performance controller having a performance register, the performance register having a plurality of values associated with incrementally increasing performance and incrementally increasing power consumption;
a high speed bus coupled to a low power static random access memory (LPSRAM), a high speed static random access memory (HSSRAM), and to the CPU;
a low speed bus coupled to the CPU and the performance register, the low speed bus coupled to an RF energy detector periodically storing samples of RF energy level into the LPSRAM;
a bridge coupling the high speed bus to the low speed bus;
the performance controller, for each discrete value of performance register, associating a CPU voltage from a CPU voltage source, a CPU clock speed from a CPU clock source, and enabling or disabling the LPSRAM and HSSRAM;
the CPU periodically waking up to examine the RF energy level samples in the LPSRAM and changing the performance register to a value associated with a higher performance level when the RF energy level samples indicate an increase in RF energy level.
10. The processor of claim 9 where said CPU voltage source for a low power performance register value is a linear regulator and a switching regulator when the performance register has a high performance value.
11. The processor of claim 9 where said CPU is coupled to a clock source which is at least one of a ring oscillator (RO) or a resistor/capacitor (RC) oscillator for a low power performance register value and a phase locked loop (PLL) oscillator for a high performance mode.
12. The processor of claim 9 where said performance register has values of PS0, PS1, PS2, PS3, and PS4, where, in sequence, each value provides greater power consumption and greater performance.
13. The processor of claim 9 where increasing the value in the performance register causes the CPU voltage and CPU clock to increase in sequence from approximately 0.7V and approximately 32 Mhz to approximately 0.9V and approximately 100 Mhz, and to approximately 1.1V and approximately 180 Mhz.
14. The processor of claim 12 where at least one of the performance register states provides a reduced HPSRAM or LPSRAM voltage for retention of data but where the reduced voltage does not provide for reading or writing data.