Multicore shared cache operation engine
Techniques for accessing memory by a memory controller, comprising receiving, by the memory controller, a memory management command to perform a memory management operation at a virtual memory address, translating the virtual memory address to a physical memory address, wherein the physical memory address comprises an address within a cache memory, and outputting an instruction to the cache memory based on the memory management command and the physical memory address.
1. A processing system comprising:
one or more processors;
a cache memory coupled to the one or more processors; and
a memory controller comprising:
circuitry configured to receive, on one of a plurality of interfaces, a memory management command to perform a memory management operation at a virtual memory address, wherein the memory controller is configured to determine a memory access command type based on the memory management command and the one of the plurality of interfaces that received the memory management command;
address translation circuity configured to translate the virtual memory address to a physical memory address, wherein the physical memory address comprises an address within the cache memory;
memory access circuitry configured to output an instruction to the cache memory based on the memory management command and the physical memory address; and
return messaging circuitry configured to:
receive a response to the instruction to the cache memory;
format the response based on the memory access command type into a formatted response; and
output the formatted response.
2. The processing system of claim 1 , wherein the processing system includes two or more processors and the cache memory is a level 2 cache shared between at least two of the two or more processors.
3. The processing system of claim 1 , wherein the cache memory comprises an internal cache memory of the memory controller.
4. The processing system of claim 1 , wherein the cache memory comprises a cache memory external to the memory controller and controlled by the memory controller.
5. The processing system of claim 1 , wherein the plurality of interfaces includes a memory mapped register of the memory controller.
6. The processing system of claim 1 , wherein the plurality of interfaces includes a shared messaging interface.
7. The processing system of claim 1 , wherein the memory access command type comprises a read command and wherein the response is formatted for output on a packet streaming interface link.
8. The processing system of claim 1 , wherein formatting the response comprises formatting a local event based on the response.
9. A memory controller device comprising:
a processor interface coupled to one or more processor cores;
circuitry configured to receive, on one of a plurality of interfaces, a memory management command to perform a memory management operation at a virtual memory address, wherein the memory controller is configured to determine a memory access command type based on the memory management command and the one of the plurality of interfaces that received the memory management command;
address translation circuity configured to translate the virtual memory address to a physical memory address of a cache memory of a processor core coupled to the processor interface;
memory access circuitry configured to output an instruction to the processor interface based on the memory management command and the physical memory address . and
return messaging circuitry configured to:
receive a response to the instruction to the cache memory;
format the response based on the memory access command type into a formatted response; and
output the formatted response.
10. The memory controller device of claim 9 , wherein the processor interface is coupled to two or more processor cores and the cache memory is a level 2 cache shared between at least two of the two or more processor cores.
11. The memory controller device of claim 9 , wherein the cache memory comprises an internal cache memory of the memory controller.
12. The memory controller device of claim 9 , wherein the cache memory comprises an external cache memory controlled by the memory controller.
13. The memory controller device of claim 9 , wherein the the plurality of interfaces includes a memory mapped register of the memory controller.
14. The memory controller device of claim 9 , wherein the plurality of interfaces includes a shared messaging interface.
15. The memory controller device of claim 9 , wherein the memory access command type comprises a read command and wherein the response is formatted for output on a packet streaming interface link shared messaging interface.
16. The memory controller device of 9 , wherein formatting the response comprises formatting a local event based on the response.
17. A method for accessing memory by a memory controller, comprising:
receiving, by the memory controller on one of a plurality of interfaces, a memory management command to perform a memory management operation at a virtual memory address, wherein the memory controller is configured to determine a memory access command type based on the memory management command and the one of the plurality of interfaces that received the memory management command;
translating the virtual memory address to a physical memory address, wherein the physical memory address comprises an address within a cache memory;
outputting an instruction to the cache memory based on the memory management command and the physical memory address;
receiving a response to the instruction to the cache memory;
format the response based on the memory access command type into a formatted response; and
outputting the formatted response.
18. The method of claim 17 , further comprising:
detecting a first one or more triggering events; and
triggering a first memory management command based on the detected first one or more triggering events.