Peak-to-average power ratio reduction for IQ transmitters

1. A method configured to clip a signal according to a clipping boundary, wherein the signal comprises an I component comprising a series of I values and a Q component comprising a series of Q values, wherein each I value and Q value pair defines Cartesian coordinates of a data point being transmitted on the real and imaginary axes of the complex plane, respectively, the method comprising:

receiving an I value and a Q value;

determining a magnitude of the I value;

determining a magnitude of the Q value; and

determining a clipping error as a distance between a first point defined by the magnitude of the I value and the magnitude of the Q value and a nearest point on the clipping boundary to the first point;

combining the clipping error with the I value to generate a clipped I value;

combining the clipping error with the Q value to generate a clipped Q value; and

providing the clipped I value and the clipped Q value to a radio frequency digital-to-analog converter (RFDAC) in a transmit chain.

2. The method of claim 1 , wherein determining the clipping error comprises determining a vector difference between a point defined by the I value and the Q value and a nearest point on the clipping boundary.

3. The method of claim 1 , further comprising:

filtering the clipping error to generate a filtered clipping error, and wherein the combining comprises:

combining the filtered clipping error with the I value; and

combining the filtered clipping error with the Q value.

4. The method of claim 1 , wherein:

combining the clipping error with the I value comprises:

applying a sign of the I value to the clipping error to generate a first signed clipping error; and

subtracting the first signed clipping error from the I value; and

combining the clipping error with the Q value comprises:

applying a sign of the Q value to the clipping error to generate a second signed clipping error; and

subtracting the second signed clipping error from the Q value.

5. The method of claim 4 , comprising:

delaying the I value to generate a delayed I value;

subtracting the first signed clipping error from the delayed I value;

delaying the Q value to generate a delayed Q value; and

subtracting the second signed clipping error from the delayed Q value.

6. The method of claim 1 , further comprising, if a clipped I value or a clipped Q value exceeds a hard clipping limit, subsequently clipping the clipped I value or the clipped Q value that exceeds the hard clipping limit.

7. The method of claim 1 , further comprising determining the clipping error to be zero in response to determining that a point defined by the I value and the Q value falls within the clipping boundary.

8. A peak-to-average power ratio (PAPR) reduction circuitry configured to clip a signal according to a clipping boundary, wherein the signal comprises an I component comprising a series of I values and a Q component comprising a series of Q values, wherein each I value and Q value pair defines Cartesian coordinates of a data point being transmitted on the real and imaginary axes of the complex plane, respectively, the PAPR reduction circuitry comprising:

clipping circuitry configured to:

receive an I value and a Q value;

determine a magnitude of the I value;

determine a magnitude of the Q value; and

determine a clipping error as a distance between a first point defined by the magnitude of the I value and the magnitude of the Q value and a nearest point on the clipping boundary to the first point; and

combination circuitry configured to:

combine the clipping error with the I value to generate a clipped I value;

combine the clipping error with the Q value to generate a clipped Q value; and

provide the clipped I value and the clipped Q value to a radio frequency digital-to-analog converter (RFDAC) in a transmit chain.

9. The PAPR reduction circuitry of claim 8 , wherein the clipping circuitry is configured to determine the clipping error by determining a vector difference between a point defined by the I value and the Q value and a nearest point on the clipping boundary.

10. The PAPR reduction circuitry of claim 8 , further comprising filter circuitry configured to filter the clipping error to generate a filtered clipping error, and wherein the combination circuitry is configured to combine the filtered clipping error with the I value and combine the filtered clipping error with the Q value.

11. The PAPR reduction circuitry of claim 8 , wherein:

the combination circuitry is configured to:

apply a sign of the I value to the clipping error to generate a first signed clipping error; and

subtract the first signed clipping error from the I value; and

apply a sign of the Q value to the clipping error to generate a second signed clipping error; and

subtract the second signed clipping error from the Q value.

12. The PAPR reduction circuitry of claim 11 , wherein the combination circuitry is configured to:

delay the I value to generate a delayed I value;

subtract the first signed clipping error from the delayed I value;

delay the Q value to generate a delayed Q value; and

subtract the second signed clipping error from the delayed Q value.

13. The PAPR reduction circuitry of claim 8 , further comprising the RFDAC, and wherein the RFDAC is configured to subsequently clip a clipped I value or a clipped Q value that exceeds a hard clipping limit.

14. The PAPR reduction circuitry of claim 8 , wherein the clipping circuitry is configured to determine the clipping error as zero in response to determining that a point defined by the I value and the Q value falls within the clipping boundary.

15. A transmitter, comprising:

a peak-to-average power ratio (PAPR) reduction circuitry configured to:

receive an I value and a Q value, wherein the I value and Q value define Cartesian coordinates of a data point being transmitted on the real and imaginary axes of the complex plane, respectively;

determine a magnitude of the I value;

determine a magnitude of the Q value;

determine a clipping error as a distance between a first point defined by the magnitude of the I value and the magnitude of the Q value and a nearest point on a clipping boundary to the first point;

combine the clipping error with the I value to generate a clipped I value; and

combine the clipping error with the Q value to generate a clipped Q value; and

a radio frequency digital-to-analog converter (RFDAC) configured to:

receive the clipped I value and the clipped Q value; and

generate an analog transmit signal based on the clipped I value and the clipped Q value.

16. The transmitter of claim 15 , wherein the PAPR reduction circuitry is further configured to:

filter the clipping error to generate a filtered clipping error;

combine the filtered clipping error with the I value; and

combine the filtered clipping error with the Q value.

17. The transmitter of claim 15 , wherein the PAPR reduction circuitry is further configured to:

determine the clipping error as zero in response to determining that a point defined by the I value and the Q value falls within the clipping boundary;

apply a sign of the I value to the clipping error to generate a first signed clipping error;

delay the I value to generate a delayed I value;

subtract the first signed clipping error from the delayed I value;

apply a sign of the Q value to the clipping error to generate a second signed clipping error;

delay the Q value to generate a delayed Q value; and

subtract the second signed clipping error from the Q value.

18. The transmitter of claim 15 , wherein the RFDAC is configured to subsequently clip the clipped I value or the clipped Q value if the clipped I value or the clipped Q value exceeds a hard clipping limit.