IP Library Granted Patent US 11,112,628
Granted Patent B2
US 11,112,628 · App. 16/609,586 · Granted Sep 7, 2021

Liquid crystal display device including common electrode control circuit

Inventors: Yuta Ueyama (Sakai, JP); Masami Ozaki (Sakai, JP); Hideki Morii (Sakai, JP)
Assignee: SHARP KABUSHIKI KAISHA
G02F1/13306G02F1/13439G02F2201/121G02F2202/10
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Quick Facts
Patent No.
US 11,112,628
App. No.
16/609,586
Granted
Sep 7, 2021
Kind
B2
Abstract

A charge pull-out period is set after power off, and an all-on control signal is set to a high level in the charge pull-out period. A high-level voltage which is output to a scanning line drive circuit formed on a liquid crystal panel is kept at a high level even after power off until a middle of the charge pull-out period. A common electrode control circuit for connecting a common electrode to a ground when the all-on control signal is at the high level and the high-level voltage is at an operation level is configured using two resistors, a NOT circuit, and two FETs, and is provided to a liquid crystal display device. With this, a liquid crystal display device which can lower a common electrode voltage to a ground level when power off and can prevent burn-in after power on is provided.

Claims (20)

1. A liquid crystal display device comprising:

a liquid crystal panel having a common electrode and formed using oxide semiconductor;

a power supply control circuit configured to output a control signal which becomes an active level in a period set after power off, and a power supply voltage which is kept at an operation level even after power off until a middle of the period; and

a common electrode control circuit configured to connect the common electrode to a ground when the control signal is at the active level and the power supply voltage is at the operation level, wherein

the common electrode control circuit includes:

a first resistor having one end to which the power supply voltage is supplied and another end connected to a first node;

a second resister having one end connected to the first node and another end connected to the ground;

a NOT circuit configured to output an inverted signal of the control signal;

a first transistor having a first conduction terminal connected to the first node, a second conduction terminal connected to the ground, and a control terminal to which the inverted signal is supplied; and

a second transistor having a first conduction terminal connected to the common electrode, a second conduction terminal connected to the ground, and a control terminal connected to the first node.

2. The liquid crystal display device according to claim 1 , wherein

the liquid crystal panel has scanning lines, and

the control signal is an all-on control signal for selecting all of the scanning lines.

3. The liquid crystal display device according to claim 2 , wherein

a scanning line drive circuit configured to drive the scanning lines is formed on the liquid crystal panel, and

the power supply voltage is a high-level voltage which is output to the scanning line drive circuit.

4. The liquid crystal display device according to claim 2 , wherein the power supply voltage is equal to or more than 5 V.

5. The liquid crystal display device according to claim 2 , wherein

the period is a charge pull-out period, and

the all-on control signal becomes a high level in the charge pull-out period.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 30, 2019
From: UEYAMA, YUTA; OZAKI, MASAMI; MORII, HIDEKI
To: SHARP KABUSHIKI KAISHA
Reel/Frame 050864/0569 →
Priority Claims (1)
JP JP2017-118260 · Jun 16, 2017 · national
Continuity (1)
Related Publication 20200150475A1 · May 14, 2020