IP Library Granted Patent US 11,245,403
Granted Patent B2
US 11,245,403 · App. 16/618,427 · Granted Feb 8, 2022

Method and a system for calibrating a phase nonlinearity of a digital-to-time converter

Inventors: Sebastian Sievert (Munich, DE); Ofir Degani (Nes-Ammin, IL); Ashoke Ravi (Portland, OR)
Assignee: INTEL CORPORATION
H03L7/085G04F10/005H03M1/1009H03M1/1071
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Quick Facts
Patent No.
US 11,245,403
App. No.
16/618,427
Granted
Feb 8, 2022
Kind
B2
Abstract

A method for calibrating a phase nonlinearity of a digital-to-time converter is provided. The method includes generating, based on a control word, a reference signal using a phase-locked loop. A frequency of the reference signal is equal to a frequency of an output signal of the digital-to-time converter. Further, the method includes measuring a temporal order of a transition of the output signal from a first signal level to a second signal level, and a transition of the reference signal from the first signal level to the second signal level. The method additionally includes adjusting a first entry of a look-up table based on the measured temporal order.

Claims (52)

1. A method for calibrating a phase nonlinearity of a digital-to-time converter, comprising:

generating, based on a control word, a reference signal using a phase-locked loop, wherein a frequency of the reference signal is substantially equal to a frequency of an output signal of the digital-to-time converter;

measuring a temporal order of a transition of the output signal from a first signal level to a second signal level, and a transition of the reference signal from the first signal level to the second signal level, wherein the temporal order indicates which of the output signal and the reference signal switches first from the first signal level to the second signal level; and

adjusting a first entry of a look-up table based on the measured temporal order.

2. The method of claim 1 , wherein the digital-to-time converter generates the output signal based on the first entry of the look-up table, and wherein the first entry is assigned to a first control code for the digital-to-time converter which is based on the control word for controlling the frequency of the output signal.

3. The method of claim 2 , further comprising:

measuring a phase error of the reference signal with respect to a phase of the output signal generated by the digital-to-time converter based on a second entry in the look-up table, wherein the second entry is assigned to a second control code for the digital-to-time converter for which the digital-to-time converter is phase linear; and

generating a correction code based on the phase offset, wherein the first control code is further based on the correction code.

4. The method of claim 1 , further comprising:

adjusting a phase of the reference signal to be substantially equal to a phase of the output signal generated by the digital-to-time converter based on a second entry in the look-up table, wherein the second entry is assigned to a second control code for the digital-to-time converter for which the digital-to-time converter is phase linear.

5. The method of claim 4 , wherein generating the reference signal is further based on a frequency control word, and wherein adjusting the phase of the reference signal comprises:

measuring, for the second entry, a third temporal order of a transition of the output signal from the first signal level to the second signal level, and a transition of the reference signal from the first signal level to the second signal level; and

generating the frequency control word based on the third temporal order.

6. The method of claim 5 , wherein adjusting the frequency control word comprises:

calculating, based on the third temporal order, a phase error of the reference signal with respect to the output signal; and

adjusting the frequency control word based on the phase error.

7. The method of claim 1 , wherein measuring the temporal order comprises measuring a predetermined number of temporal orders, and wherein adjusting the first entry is based on the predetermined number of temporal orders.

8. The method of claim 7 , wherein at least part of the predetermined number of temporal orders is measured in parallel.

9. The method of claim 7 , wherein adjusting the first entry based on the predetermined number of temporal orders comprises:

deriving an indicator value from the predetermined number of temporal orders which indicates whether the transition of the output signal from the first signal level to the second signal level, or the transition of the reference signal from the first signal level to the second signal level is leading the other one more often among the predetermined number of temporal orders; and

adjusting the first entry based on the indicator value.

10. The method of claim 9 , wherein the first entry is only adjusted if the absolute value of the indicator value is greater than a threshold value.

11. The method of claim 7 , wherein measuring the predetermined number of temporal orders and adjusting the first entry based on the predetermined number of temporal orders is carried out iteratively.

12. The method of claim 11 , wherein the digital-to-time converter generates the output signal based on further entries in the look-up table, the further entries being assigned to further control codes for the digital-to-time converter, and wherein the method further comprises:

measuring, for the further entries, a respective temporal order of the transition of the output signal from the first signal level to the second signal level, and the transition of the reference signal from the first signal level to the second signal level; and

adjusting the further entries based on the respective temporal order.

13. The method of claim 12 , wherein measuring the respective temporal order for the further entries is carried out a predetermined number of times so that a respective predetermined number of temporal orders is measured for each of the further entries, and wherein adjusting the further entries is based on the respective predetermined number of temporal orders.

14. The method of claim 13 , wherein measuring the respective predetermined number of temporal orders for the first and the further entries of the look-up table, and adjusting the first and the further entries is carried out iteratively until a maximum number of iterations is reached or each of the first and the further entries satisfies a quality criterion.

15. The method of claim 11 , wherein iteratively adjusting the first entry comprises:

incrementing or decrementing the first entry in the first iteration by a first value based on the predetermined number of temporal orders of the first iteration; and

incrementing or decrementing the first entry in the second iteration by a second value based on the predetermined number of temporal orders of the second iteration, wherein the second value is substantially half of the first value.

16. The method of claim 1 , further comprising:

measuring, for the first entry, a second temporal order of a transition of the output signal from the second signal level to the first signal level, and a transition of the reference signal from the second signal level to the first signal level,

wherein adjusting the first entry is further based on the second temporal order.

17. The method of claim 1 , wherein adjusting the first entry comprises:

incrementing or decrementing the first entry based on the first temporal order.

18. A system for calibrating a phase nonlinearity of a digital-to-time converter, comprising:

a phase-locked loop configured to generate, based on a control word, a reference signal, wherein a frequency of the reference signal is substantially equal to a frequency of an output signal of the digital-to-time converter;

a detection circuit configured to measure a temporal order of a transition of the output signal from a first signal level to a second signal level, and a transition of the reference signal from the first signal level to the second signal level, wherein the temporal order indicates which of the output signal and the reference signal switches first from the first signal level to the second signal level; and

a processing circuit configured to adjust a first entry of a look-up table based on the measured temporal order.

19. The system of claim 18 , wherein the digital-to-time converter generates the output signal based on the first entry of the look-up table, wherein the first entry is assigned to a first control code for the digital-to-time converter which is based on the control word for controlling the frequency of the output signal.

20. The system of claim 18 , wherein the phase-locked loop is configured to adjust a phase of the reference signal to be substantially equal to a phase of the output signal generated by the digital-to-time converter based on a second entry in the look-up table, wherein the second entry is assigned to a second control code for the digital-to-time converter for which the digital-to-time converter is phase linear.

21. The system of claim 20 , wherein:

the phase-locked loop is further configured to generate the reference signal based on a frequency control word,

the detection circuit is further configured to measure, for the second entry, a third temporal order of a transition of the output signal from the first signal level to the second signal level, and a transition of the reference signal from the first signal level to the second signal level; and

the system further comprises a conversion circuit configured to generate the frequency control word based on the third temporal order.

22. The system of claim 18 , wherein the detection circuit is further configured to measure a predetermined number of temporal orders, and wherein the processing circuit is further configured to adjust the first entry based on the predetermined number of temporal orders.

23. The system of claim 22 , wherein the processing circuit is further configured to:

derive an indicator value from the predetermined number of temporal orders which indicates whether the transition of the output signal from the first signal level to the second signal level, or the transition of the reference signal from the first signal level to the second signal level is leading the other one more often among the predetermined number of temporal orders; and

adjust the first entry based on the indicator value.

24. The system of claim 23 , wherein the processing circuit is further configured to adjust the first entry only if the absolute value of the indicator value is greater than a threshold value.

25. A receiver comprising a digital-to-time converter and a system for calibrating a phase nonlinearity of the digital-to-time converter according to claim 18 .

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 8, 2021
From: INTEL IP CORPORATION
To: INTEL CORPORATION
Reel/Frame 056524/0373 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 2, 2019
From: SIEVERT, SEBASTIAN; DEGANI, OFIR; RAVI, ASHOKE
To: INTEL IP CORPORATION
Reel/Frame 051147/0707 →