Pixel structure and method for driving the same, display panel and display apparatus
A pixel structure is disclosed. The pixel structure includes: a plurality of scanning lines; a plurality of data lines intersecting the plurality of scanning lines; and a plurality of sub-pixels which are located at respective intersections of the plurality of scanning lines and the plurality of data lines and are arranged in rows and columns. (4n+1) th and (4n+2) th data lines of the plurality of data lines are located on opposite sides of a (2n+1) th column of sub-pixels respectively. (4n+3) th and (4n+4) th data lines of the plurality of data lines are located on opposite sides of a (2n+2) th column of sub-pixels respectively. The (4n+2) th and (4n+3) th data lines of the plurality of data lines are located between the (2n+1) th column of sub-pixels and the (2n+2) th column of sub-pixels, where n is an integer greater than or equal to 0.
1. A display apparatus, comprising:
a plurality of scanning lines;
a plurality of data lines intersecting the plurality of scanning lines; and
a plurality of sub-pixels which are located at respective intersections of the plurality of scanning lines and the plurality of data lines and are arranged in rows and columns,
wherein (4n+1) th and (4n+2) th data lines of the plurality of data lines are located on opposite sides of a (2n+1) th column of sub-pixels respectively,
(4n+3) th and (4n+4) th data lines of the plurality of data lines are located on opposite sides of a (2n+2) th column of sub-pixels respectively,
the (4n+2) th and (4n+3) th data lines of the plurality of data lines are located between the (2n+1) th column of sub-pixels and the (2n+2) th column of sub-pixels, where n is an integer greater than or equal to 0, and
the (4n+1) th , (4n+2) th , (4n+3) th , and (4n+4) th data lines of the plurality of data lines have a configuration selected from a group consisting of:
(i) the (4n+1) th data line of the plurality of data lines is connected to odd-numbered rows of sub-pixels in the (2n+1) th column of sub-pixels, the (4n+2) th data line of the plurality of data lines is connected to even-numbered rows of sub-pixels in the (2n+1) th column of sub-pixels, the (4n+3) th data line of the plurality of data lines is connected to even-numbered rows of sub-pixels in the (2n+2) th column of sub-pixels, and the (4n+4) th data line of the plurality of data lines is connected to odd-numbered rows of sub-pixels in the (2n+2) th column of sub-pixels; and
(ii) the (4n+1) th data line of the plurality of data lines is connected to the even-numbered rows of sub-pixels in the (2n+1) th column of sub-pixels, the (4n+2) th data line of the plurality of data lines is connected to the odd-numbered rows of sub-pixels in the (2n+1) th column of sub-pixels, the (4n+3) th data line of the plurality of data lines is connected to the odd-numbered rows of sub-pixels in the (2n+2) th column of sub-pixels, and the (4n+4) th data line of the plurality of data lines is connected to the even-numbered rows of sub-pixels in the (2n+2) th column of sub-pixels;
further comprising:
a scanning driver configured to sequentially supply a scanning signal to the plurality of scanning lines;
a data driver configured to generate a plurality of analog data signals from a digital image signal; and
a demultiplexer configured to receive the plurality oi analog data signals from the data driver, supply the analog data signals to the (4n+1)th and (4n+4)th data lines of the plurality of data lines in a first period, and supply the analog data signals to the (4n+2)th and (4n+3)th data lines of the plurality of data lines in a second period different from the first period,
wherein the demultiplexer comprises a plurality of transistors, wherein:
(4n+1)th, (4n+2)th, (4n+3)th, and (4n+4)th transistors of the plurality of transistors connect the (4n+1)th, (4n+2)th, (4n+3)th, and (4n+4)th data lines of the plurality of data lines to the data driver respectively,
the (4n+1)th and (4n+2)th transistors of the plurality of transistors are connected to the same output terminal of the data driver, and
the (4n+3)th and (4n+4)th transistors of the plurality of transistors are connected to the same output terminal of the data driver.
2. The display apparatus according to claim 1 , wherein
the (4n+1) th and (4n+2) th data lines of the plurality of data lines are symmetrically located on opposite sides of the (2n+1) th column of sub-pixels, and
the (4n+3) th and (4n+4) th data lines of the plurality of data lines are symmetrically located on opposite sides of the (2n+2) th column of sub-pixels.
3. The display apparatus according to claim 1 , wherein
a distance between the (4n+1) th data line and the (4n+2) th data line of the plurality of data lines is greater than a threshold distance, and
a distance between the (4n+3) th data line and the (4n+4) th data line of the plurality of data lines is greater than the threshold distance.
4. The display apparatus according to claim 1 , wherein the plurality of data lines are disposed in the same layer.
5. The display apparatus according to claim 1 , further comprising:
a plurality of power lines each connected to a corresponding column of sub-pixels of the respective columns of sub-pixels,
wherein a (2n+1) th power line of the plurality of power lines is located between the (4n+1) th data line and the (4n+2) th data line of the plurality of data lines, and
a (2n+2) th power line of the plurality of power lines is located between the (4n+3) th data line and the (4n+4) th data line of the plurality of data lines.
6. The display apparatus according to claim 5 , wherein the plurality of power lines are disposed in the same layer as the plurality of data lines.
7. The display apparatus according to claim 1 , wherein the plurality of data lines are made of the same material.
8. The display apparatus according to claim 1 , wherein
the (4n+1) th and (4n+4) th transistors of the plurality of transistors are configured to be turned on in the first period, and
the (4n+2) th and (4n+3) th transistors of the plurality of transistors are configured to be turned on in the second period.
9. The display apparatus according to claim 1 , further comprising:
a plurality of light-emitting control lines, wherein each of the light-emitting control lines is connected to a corresponding row of sub-pixels of the respective rows of sub-pixels; and
a light-emitting control driver configured to sequentially supply a light-emitting control signal to the plurality of light-emitting control lines, wherein (2i+1) th and (2i+2) th rows of sub-pixels in the respective rows of sub-pixels are supplied with the same light-emitting control signal to be enabled to emit light at the same time, where i is an integer greater than or equal to 0.
10. A method for driving the display apparatus according to claim 1 , wherein the pixel structure further comprises a plurality of light-emitting control lines, wherein each of the light-emitting control lines is connected to a corresponding row of sub-pixels of the respective rows of sub-pixels, the method comprising:
sequentially supplying, by a light-emitting control driver, a light-emitting control signal to the plurality of light-emitting control lines,
wherein (2i+1) th and (2i+2) th rows of sub-pixels in the respective rows of sub-pixels are supplied with the same light-emitting control signal to be enabled to emit light at the same time, where i is an integer greater than or equal to 0.