Collision handling of synchronization signal (SS) blocks

1. An apparatus:

processing circuitry, the processing circuitry configured to cause a user equipment (UE) to:

decode synchronization information within a synchronization signal (SS) block, the SS block received within a SS burst set and occupying a subset of a plurality of Orthogonal Frequency Division Multiplexing (OFDM) symbols within a slot, wherein at least one of the symbols in the subset coincides with a pre-defined symbol location associated with a demodulation reference signal (DM-RS) of a physical downlink shared channel (PDSCH);

perform a synchronization procedure with a next generation Node-B (gNB) based on the synchronization information within the SS block;

detect the DM-RS within the slot, the DM-RS starting at a symbol location that is shifted from the pre-defined symbol location and following the subset of symbols; and

decode downlink data received via the PDSCH and based on the detected DM-RS.

2. The apparatus of claim 1 , wherein the DM-RS is a front-loaded DM-RS with the pre-defined symbol location at a beginning of the slot.

3. The apparatus of claim 1 , wherein the downlink DM-RS occupies one of a single symbol or two symbols within the slot, starting at the pre-defined symbol location within the PD SCH transmission.

4. The apparatus of claim 1 , wherein the processing circuitry is configured to:

detect a first portion of the DM-RS at a first plurality of physical resource blocks (PRBs) starting at the pre-defined symbol location; and

detect a remaining portion of the DM-RS at a second plurality of PRBs starting at the shifted symbol location.

5. The apparatus of claim 1 , wherein the processing circuitry is configured to:

detect a first portion of the DM-RS at a first plurality of physical resource blocks (PRBs) starting at the pre-defined symbol location; and

detect the SS block at a second plurality of PRBs starting at the pre-defined symbol location.

6. The apparatus of claim 5 , wherein the processing circuitry is configured to:

detect a second DM-RS within the slot, the second DM-RS starting at a second symbol location following an end symbol of the SS block; and

refrain from decoding a portion of the downlink data received via the second plurality of PRBs, the portion of the downlink data located after the end symbol of the SS block and prior to the second symbol location.

7. The apparatus of claim 5 , wherein the processing circuitry is configured to:

detect a second DM-RS within the slot, the second DM-RS starting at a second symbol location following an end symbol of the SS block;

refrain from decoding a portion of the downlink data received via the second plurality of PRBs, the portion of the downlink data located after the end symbol of the SS block and prior to at least two symbols before the second symbol location; and

decode a second portion of the downlink data received within the slot, the second portion located after the end of the portion of downlink data that is undecoded and before the second symbol location.

8. The apparatus of claim 7 , wherein the processing circuitry is configured to:

buffer the second portion of the downlink data; and

decode the second portion of the downlink data using the second DM-RS.

9. The apparatus of claim 1 , wherein a number of SS blocks within the SS burst set per frame and the locations of the SS blocks within the frame are based on a subcarrier spacing.

10. The apparatus of claim 1 , wherein the subset of OFDM symbols comprises four consecutive OFDM symbols, including a first OFDM symbol, a second OFDM symbol, a third OFDM symbol, and a fourth OFDM symbol.

11. The apparatus of claim 10 , wherein

the first OFDM symbol of the SS block comprises a primary synchronization signal (PSS),

the second OFDM symbol of the SS block and the fourth OFDM symbol of the SS block comprise a physical broadcast channel (PBCH), and

the third OFDM symbol of the SS block comprises a secondary synchronization signal (SSS) and the PBCH.

12. An apparatus comprising:

processing circuitry, configured to cause a Next Generation Node B (gNB) to:

encode synchronization information within a synchronization signal (SS) block for transmission to a user equipment (UE) within a SS burst set, the SS block occupying a subset of a plurality of Orthogonal Frequency Division Multiplexing (OFDM) symbols within a slot, wherein at least one of the symbols in the subset coincides with a pre-defined symbol location associated with a demodulation reference signal (DM-RS) of a physical downlink shared channel (PDSCH);

encode the DM-RS for transmission within the slot, the DM-RS starting at a symbol location that is shifted from the p re-defined symbol location and following the subset of symbols; and

encode downlink data for transmission via the PDSCH and based on the DM-RS.

13. The apparatus of claim 12 , wherein the processing circuitry is configured to:

encode a physical downlink control channel (PDCCH) for transmission via a resource within a control resource set (CORESET), wherein the CORESET is rate-matched around one or more symbols of the SS block.

14. The apparatus of claim 13 , wherein the CORESET overlaps at least partially with the SS block, and the processing circuitry is configured to:

perform resource element group (REG)-to-control channel element (CCE) mapping based on pre-defined time and frequency domain dimensions of the CORESET.

15. The apparatus of claim 14 , wherein at least one REG of a plurality of REGs within the CORESET is punctured based on the overlap, and wherein the processing circuitry is configured to:

encode downlink control information (DCI) within the PDCCH, wherein one or more symbols of the DCI are rate-matched on the resource based on aggregation of one or more CCEs due to the punctured at least one REG.

16. The apparatus of claim 15 , wherein the processing circuitry is configured to:

adjust aggregation level (AL) for the PDCCH based on a puncturing level associated with the at least one punctured REG.

17. The apparatus of claim 14 , wherein the processing circuitry is configured to:

perform the REG-to-CCE mapping based on allocating a fixed number of REGs per CCE.

18. The apparatus of claim 14 , wherein one or more positions of the CORSET and the SS block overlap in frequency domain.

19. The apparatus of claim 14 , wherein the subset of OFDM symbols comprises four consecutive OFDM symbols, including a first OFDM symbol, a second OFDM symbol, a third OFDM symbol, and a fourth OFDM symbol.

20. A non-transitory computer-readable storage medium that stores instructions for execution by one or more processors of a user equipment (UE), the instructions to configure the one or more processors to cause the UE to:

decode synchronization information within a synchronization signal (SS) block, the SS block received within a SS burst set and occupying a subset of a plurality of Orthogonal Frequency Division Multiplexing (OFDM) symbols within a slot, wherein at least one of the symbols in the subset coincides with a pre-defined symbol location associated with a demodulation reference signal (DM-RS) of a physical downlink shared channel (PDSCH), and wherein the downlink DM-RS occupies one of a single symbol or two symbols within the slot, starting at the pre-defined symbol location;

perform a synchronization procedure with a next generation Node-B (gNB) based on the synchronization information within the SS block;

detect the DM-RS within the slot, the DM-RS starting at a symbol location that is shifted from the pre-defined symbol location and following the subset of symbols; and

decode downlink data received via the PDSCH and based on the detected DM-RS.