Collision handling of reference signals

1. An apparatus of a user equipment (UE), the apparatus comprising:

processing circuitry, the processing circuitry configured to:

decode control information of a physical downlink control channel (PDCCH) received via a resource within a control resource set (CORESET) occupying a subset of a plurality of Orthogonal Frequency Division Multiplexing (OFDM) symbols within a slot, wherein at least one of the symbols in the subset coincides with a pre-defined symbol location associated with a demodulation reference signal (DM-RS) of a physical downlink shared channel (PDSCH);

detect the DM-RS within the slot, the DM-RS starting at a symbol location that is shifted from the p re-defined symbol location and following the subset of symbols; and

decode downlink data scheduled by the PDCCH and received via the PDSCH, the decoding based on the detected DM-RS; and

memory coupled to the processing circuitry, the memory configured to store the control information.

2. The apparatus of claim 1 , wherein the DM-RS is a full DM-RS, occupying a same number of physical resource blocks (PRBs) as the CORESET.

3. The apparatus of claim 1 , wherein the DM-RS is shifted by zero or more OFDM symbols.

4. The apparatus of claim 1 , wherein the DM-RS is a front-loaded DM-R.S with the pre-defined symbol location at a first symbol of the PDSCH duration.

5. The apparatus of claim 1 , wherein the downlink DM-RS occupies one of a single symbol or two symbols within the slot, starting at the pre-defined symbol location within the PDSCH transmission.

6. The apparatus of claim 1 , wherein the processing circuitry is configured to:

detect a first portion of the DM-RS at a first plurality of physical resource blocks (PRBs) starting at the pre-defined symbol location; and

detect a remaining portion of the DM-RS at a second plurality of PRBs starting at the shifted symbol location.

7. The apparatus of claim 1 , wherein the processing circuitry is configured to:

detect a first portion of the DM-RS at a first plurality of physical resource blocks (PRBs) starting at the pre-defined symbol location; and

detect the CORESET at a second plurality of PRBs starting at the pre-defined symbol location.

8. The apparatus of claim 7 , wherein the first portion of the DM-RS includes a complete demodulation reference signal that can be used to decode the PDSCH received within the slot.

9. The apparatus of claim 7 , wherein the processing circuitry is configured to:

detect a second DM-RS within the slot, the second DM-RS starting at a second symbol location following an end symbol of the CORESET; and

refrain from decoding a portion of the downlink data received via the second plurality of PRBs, the portion of the downlink data located after the end symbol of the CORESET and prior to the second symbol location.

10. The apparatus of claim 1 , wherein a mapping associated with the DM-RS is one of DM-RS mapping type A or DM-RS mapping type B.

11. The apparatus of claim 10 , wherein the PDSCH spans durations of 3 through 14 symbols within a slot for the mapping type A, and the PDSCH spans durations of 2, 4, or 7 symbols for the mapping type B.

12. The apparatus of claim 1 , wherein the DM-RS is shifted by zero or more symbols and the processing circuitry is configured to:

determine a minimum UE processing time from an end of reception of the PDSCH and a time instance for a start of a corresponding hybrid automatic repeat request acknowledgement (HARQ-ACK) transmission.

13. The apparatus of claim 12 , wherein the PDCCH and the PDSCH are multiplexed in frequency domain for some or all PRBs of the PDSCH, and wherein the minimum UE processing time is increased by d symbols, when the PDCCH ends d symbols after a starting symbol of the PDSCH.

14. The apparatus of claim 12 , wherein the DM-RS is mapping type B with 2-symbol duration, and wherein the minimum UE processing time is (N1+3) symbols when there is no time domain overlap between the PDCCH and the PDSCH, where N1 symbols corresponds to the minimum UE processing time for a PDSCH with mapping type A or B with duration of at least 7 symbols.

15. The apparatus of claim 12 , wherein the DM-RS is mapping type B with 2-symbol duration, and wherein the UE processing time is (N1+3+d) symbols when there is a time domain overlap of d symbols between the PDCCH and the PDSCH.

16. An apparatus of a Next Generation Node-B (gNB), the apparatus comprising:

processing circuitry, configured to:

encode control information of a physical downlink control channel (PDCCH) for transmission to a user equipment (UE) via a resource within a control resource set (CORESET), the CORESET occupying a subset of a plurality of Orthogonal Frequency Division Multiplexing (OFDM) symbols within a slot, wherein at least one of the symbols in the subset coincides with a pre-defined symbol location associated with a demodulation reference signal (DM-RS) of a physical downlink shared channel (PDSCH) scheduled by the PDCCH;

encode the DM-RS for transmission within the slot, the DM-RS starting at a symbol location that is shifted from the p re-defined symbol location and following the subset of symbols; and

encode downlink data for transmission via the PDSCH and based on the DM-RS; and

memory coupled to the processing circuitry, the memory configured to store the control information.

17. The apparatus of claim 16 , wherein the processing circuitry is configured to:

encode a first portion of the DM-RS for transmission at a first plurality of physical resource blocks (PRBs) starting at the pre-defined symbol location; and

encode a remaining portion of the DM-RS at a second plurality of PRBs starting at the shifted symbol location.

18. The apparatus of claim 16 , wherein the processing circuitry is configured to:

encode a first portion of the DM-RS at a first plurality of physical resource blocks (PRBs) starting at the pre-defined symbol location; and

encode the control information within the CORESET at a second plurality of PRBs starting at the pre-defined symbol location.

19. The apparatus of claim 18 , wherein the processing circuitry is configured to:

encode a portion of the downlink data for transmission via resources associated with the first plurality of PRBs and based on the first portion of the DM-RS.

20. A computer-readable storage medium that stores instructions for execution by one or more processors of a user equipment (UE), the instructions to configure the one or more processors to cause the UE to:

decode control information of a physical downlink control channel (PDCCH) received via a resource within a control resource set (CORESET) occupying a subset of a plurality of Orthogonal Frequency Division Multiplexing (OFDM) symbols within a slot, wherein at least one of the symbols in the subset coincides with a pre-defined symbol location associated with a demodulation reference signal (DM-RS) of a physical downlink shared channel (PDSCH);

detect the DM-RS within the slot, the DM-RS starting at a symbol location that is shifted from the pre-defined symbol location and following the subset of symbols;

decode downlink data scheduled by the PDCCH and received via the PDSCH, the decoding based on the detected DM-RS;

decode configuration information including a p ammeter indicating a minimum UE processing time from an end of reception of the downlink data and a start of a corresponding hybrid automatic rep eat request acknowledgement (HARQ-ACK) transmission; and

generate the HARQ-ACK after the end of reception of the downlink data and based on the minimum UE processing time.