Multi version library cell handling and integrated circuit structures fabricated therefrom
Multi version library cell handling and integrated circuit structures fabricated therefrom are described. In an example, an integrated circuit structure includes a plurality of gate lines parallel along a first direction of a substrate and having a pitch along a second direction orthogonal to the first direction. A first version of a cell type is over a first portion of the plurality of gate lines, the first version of the cell type including a first plurality of interconnect lines having a second pitch along the second direction, the second pitch less than the first pitch.
1. An integrated circuit structure, comprising:
a plurality of gate lines parallel along a first direction of a substrate and having a pitch along a second direction orthogonal to the first direction;
a first version of a cell type over a first portion of the plurality of gate lines, the first version of the cell type comprising a first plurality of interconnect lines having a second pitch along the second direction, the second pitch less than the first pitch; and
a second version of the cell type over a second portion of the plurality of gate lines laterally adjacent to the first version of the cell type along the second direction, the second version of the cell type comprising a second plurality of interconnect lines having the second pitch along the second direction, and the second version of the cell type structurally different than the first version of the cell type.
2. The integrated circuit structure of claim 1 , wherein individual ones of the first plurality of interconnect lines of the first version of the cell type align with individual ones of the plurality of gate lines along the first direction at both edges of the first version of the cell type along the second direction.
3. The integrated circuit structure of claim 2 , wherein the first version of the cell type is a first version of an inverter cell.
4. The integrated circuit structure of claim 1 , wherein individual ones of the second plurality of interconnect lines of the second version of the cell type do not align with individual ones of the plurality of gate lines along the first direction at both edges of the second version of the cell type along the second direction.
5. The integrated circuit structure of claim 4 , wherein the second version of the cell type is a second version of an inverter cell.
6. The integrated circuit structure of claim 1 , wherein individual ones of the first plurality of interconnect lines of the first version of the cell type align with individual ones of the plurality of gate lines along the first direction at a first edge but not at a second edge of the first version of the cell type along the second direction.
7. The integrated circuit structure of claim 6 , wherein the first version of the cell type is a first version of a NAND cell.