Array substrate, manufacturing method, display panel and display device thereof
View Patent ↗Arrangements disclosed in the present disclosure provide an array substrate, a manufacturing, a display panel and a display device. The array substrate comprises: a first signal line comprising a first extension portion along a first direction and a first connection portion along a second direction, which is provided with via holes; a second signal line comprising a second extension portion and a second connection portion along the second direction, which is provided with via holes; and a conductive connection layer, configured to connect the first signal line and the second signal line through the via holes of the first connection portion and second connection portion. The first connection portion and the second connection portion are lined up in a direction perpendicular to the second direction.
1. An array substrate, comprising:
a first signal line comprising a first extension portion in a first direction and a first connection portion in a second direction, wherein the first connection portion is provided with via holes;
a second signal line comprising a second extension portion and a second connection portion in the second direction, wherein the second connection portion is provided with via holes; and
a conductive connection layer configured to connect the first signal line and the second signal line through the via holes of the first connection portion and the via holes of the second connection portion;
wherein the first connection portion and the second connection portion are lined up in a direction perpendicular to the second direction.
2. The array substrate according to claim 1 , wherein a sum of widths of the first connection portion and the second connection portion is not greater than a width of the second extension portion.
3. The array substrate according to claim 1 , wherein an engaging structure is formed between the first connection portion and the second connection portion.
4. The array substrate according to claim 3 , wherein a shape of a neighboring boundary between the first connection portion and the second connection portion is any one or more of a square wave shape, a zigzag shape, an arc shape and an irregular shape.
5. The array substrate according to claim 1 , wherein the first signal line further comprises a third connection portion in the first direction, and the third connection portion is provided with via holes;
the second signal line further comprises a fourth connection portion in the first direction, and the fourth connection portion is provided with via holes;
the conductive connection layer is further configured to connect the first signal line and the second signal line through the via holes of the third connection portion and the via holes of the fourth connection portion; and
the third connection portion and the fourth connection portion are lined up in a direction perpendicular to the first direction.
6. The array substrate according to claim 5 , wherein a sum of widths of the third connection portion and the fourth connection portion is not greater than a width of the first extension portion.
7. The array substrate according to claim 5 , wherein an engaging structure is formed between the third connection portion and the fourth connection portion.
8. The array substrate according to claim 7 , wherein a shape of a neighboring boundary between the third connection portion and the fourth connection portion is any one or more of a square wave shape, a zigzag shape, an arc shape and an irregular shape.
9. The array substrate according to claim 1 , wherein the first signal line is a signal line in the array substrate and the second signal line is a signal lead-out line of the corresponding signal line, or the second signal line is a signal line in the array substrate and the first signal line is a signal lead-out line of the corresponding signal line.
10. The array substrate according to claim 9 , wherein the first and second signal lines comprise any one of a gate line, a data line, a common electrode line, a clock signal line and a touch line.
11. The array substrate according to claim 1 , wherein the first direction is perpendicular to the second direction.
12. A display panel, comprising the array substrate according to claim 1 .
13. A display device, comprising the display panel according to claim 12 .
14. A method for manufacturing an array substrate, comprising:
depositing a first metal layer on a substrate and forming a first signal line by the first metal layer, wherein the first signal line comprises a first extension portion in a first direction and a first connection portion in a second direction;
depositing a first insulating layer on the first metal layer, depositing a second metal layer on the first insulating layer and forming a second signal line by the second metal layer, wherein the second signal line comprises a second extension portion and a second connection portion in the second direction;
depositing a second insulating layer on the second metal layer, forming via holes of the first connection portion by penetrating the second insulating layer and the second metal layer and forming via holes of the second connection portion by penetrating the second insulating layer; and
depositing a conductive connection layer on the second insulating layer and forming a pattern of the conductive connection layer etching, wherein the first signal line and the second signal line are connected through the via holes of the first connection portion and the via holes of the second connection portion in the pattern;
wherein the first connection portion and the second connection portion are lined up in a direction perpendicular to the second direction.
15. The method for manufacturing an array substrate according to claim 14 , wherein a sum of widths of the first connection portion and the second connection portion is not greater than a width of the second extension portion.
16. The method for manufacturing an array substrate according to claim 14 , wherein an engaging structure is formed between the first connection portion and the second connection portion.
17. The method for manufacturing an array substrate according to claim 16 , wherein a shape of a neighboring boundary between the first connection portion and the second connection portion is any one or more of a square wave shape, a zigzag shape, an arc shape and an irregular shape.
18. The method for manufacturing an array substrate according to claim 14 , wherein forming the first signal line further comprises forming a third connection portion in the first direction, and third connection portion is provided with via holes;
forming the second signal line further comprises forming a fourth connection portion in the first direction, and the fourth connection portion is provided with via holes;
forming the conductive connection layer further comprises forming a pattern of the conductive connection layer by etching, wherein the first signal line and the second signal line are connected through the via holes of the third connection portion and the via holes of the fourth connection portion in the pattern; and
the third connection portion and the fourth connection portion are lined up in a direction perpendicular to the first direction.
19. The method for manufacturing an array substrate according to claim 18 , wherein a sum of widths of the third connection portion and the fourth connection portion is not greater than a width of the first extension portion.
20. The method for manufacturing an array substrate according to claim 18 , wherein an engaging structure is formed between the third connection portion and the fourth connection portion.