Quantum information processing device formation
A method for forming at least part of a quantum information processing device is presented. The method includes providing a first electrically-conductive layer formed of a first electrically-conductive material ( 100 ′) on a principal surface of a substrate ( 10 ), depositing a layer of dielectric material on the first electrically-conductive material, patterning the layer of dielectric material to form a pad of dielectric material and to reveal a first region of the first electrically-conductive layer, depositing a second electrically-conductive layer ( 104 ′) on the pad of dielectric material and on the first region of the first electrically-conductive layer, patterning the second electrically-conductive layer and removing the pad of dielectric material using isotropic gas phase etching.
1. A method, comprising:
forming at least part of a quantum information processing device, comprising:
providing a first electrically-conductive layer formed of a first electrically-conductive material on a principal surface of a substrate;
patterning the first electrically-conductive layer into a first electrically-conductive base, a second electrically-conductive base, and a center electrically-conductive strip arranged between the first electrically-conductive base and the second electrically-conductive base, wherein the center electrically-conductive strip is separated from the first electrically-conductive base and the second electrically-conductive base by a first window in the first electrically-conductive layer and a second window in the first electrically-conductive layer, respectively;
depositing a layer of dielectric material on the first electrically-conductive material;
patterning the layer of dielectric material to form a pad of dielectric material and to reveal a first region of the first electrically-conductive layer and a second region of the first electrically-conductive layer, wherein the first region is on the first electrically-conductive base and the second region is on the second electrically-conductive base;
depositing a second electrically-conductive layer on the pad of dielectric material, on the first region, and on the second region of the first electrically-conductive layer;
patterning the second electrically-conductive layer to obtain a bridge structure, wherein the bridge structure spans the center electrically-conductive strip; and
removing the pad of dielectric material using isotropic gas phase etching.
2. The method of claim 1 , wherein removing the pad of dielectric material using isotropic gas phase etching comprises:
etching at least one patterned region of dielectric material using a mixture which includes hydrogen fluoride vapour.
3. The method of claim 1 , wherein removing the pad of dielectric material using isotropic gas phase etching comprises:
etching at least one patterned region of dielectric material using a mixture which includes xenon difluoride vapour.
4. The method of claim 1 , wherein removing the pad of dielectric material using isotropic gas phase etching comprises:
etching at least one patterned region of dielectric material using plasma generated with a mixture which includes tetrafluoromethane vapour and nitrogen trifluoride vapour.
5. The method of claim 1 , wherein patterning the first electrically-conductive layer comprises:
patterning the first electrically-conductive layer so as to form the first window and the second window in the first electrically-conductive layer.
6. The method of claim 1 , wherein the substrate comprises a silicon substrate.
7. The method of claim 1 , wherein the first electrically-conductive layer is a first metallization layer.
8. The method of claim 1 , wherein the first electrically-conductive layer is superconducting below a critical temperature.
9. The method of claim 1 , wherein the first electrically-conductive layer comprises aluminium.
10. The method of claim 1 , wherein the layer of dielectric material comprises a layer of silicon dioxide.
11. The method of claim 1 , wherein the second electrically-conductive layer is a second metallization layer.
12. The method of claim 1 , wherein the second electrically-conductive layer is superconducting below a critical temperature.
13. The method of claim 1 , wherein the second electrically-conductive layer comprises aluminium.
14. The method of claim 1 , wherein forming the at least part of the quantum information processing device comprises forming a capacitor.
15. The method of claim 1 , wherein forming the at least part of the quantum information processing device comprises forming an inductor.
16. The method of claim 1 , wherein forming the at least part of the quantum information processing device comprises forming a resonator.
17. The method of claim 1 , wherein forming the at least part of the quantum information processing device includes using CMOS-compatible processing steps.
18. The method of claim 1 , wherein each of the first electrically-conductive base and the second electrically-conductive base are ground planes.
19. The method of claim 1 , further comprising patterning the first electrically-conductive layer subsequent to removing the pad of dielectric material.
20. The method of claim 1 , wherein, after obtaining the bridge structure and removing the pad of dielectric material, the first electrically-conductive layer and the second electrically-conductive layer form a capacitor of a qubit.
21. The method of claim 1 , wherein, after obtaining the bridge structure and removing the pad of dielectric material, the first electrically-conductive layer forms an inductor of a qubit and the second electrically-conductive layer forms a flux bias coil.
22. The method of claim 1 , wherein the first electrically-conductive layer is a single layer of the first electrically-conductive material.