IP Library Granted Patent US 11,380,804
Granted Patent B2
US 11,380,804 · App. 16/640,504 · Granted Jul 5, 2022

Semiconductor device with higher breakdown voltage and electronic apparatus

Inventor: Hitoshi Okano (Kanagawa, JP)
Assignee: SONY SEMICONDUCTOR SOLUTIONS CORPORATION
H01L29/868H01L27/0255H01L29/0615H01L29/0657
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Quick Facts
Patent No.
US 11,380,804
App. No.
16/640,504
Granted
Jul 5, 2022
Kind
B2
Abstract

A semiconductor device including a first conductivity-type layer into which first conductivity-type impurities are introduced, a second conductivity-type layer into which second conductivity-type impurities are introduced, the second conductivity-type impurities being different in polarity from the first conductivity-type impurities, and an intermediate layer that is sandwiched between the first conductivity-type layer and the second conductivity-type layer, and does not include the first conductivity-type impurities or the second conductivity-type impurities, or includes the first conductivity-type impurities or the second conductivity-type impurities at a concentration lower than a concentration of the first conductivity-type impurities in the first conductivity-type layer or the second conductivity-type impurities in the second conductivity-type layer, the first conductivity-type layer, the intermediate layer, and the second conductivity-type layer being stacked in a thickness direction of a semiconductor substrate inside the semiconductor substrate.

Claims (27)

1. A semiconductor device, comprising:

a first conductivity-type layer that comprises first conductivity-type impurities;

a second conductivity-type layer that comprises second conductivity-type impurities, wherein the second conductivity-type impurities are different in polarity from the first conductivity-type impurities;

an intermediate layer sandwiched between the first conductivity-type layer and the second conductivity-type layer, wherein

the intermediate layer does not include the first conductivity-type impurities or the second conductivity-type impurities, or includes one of the first conductivity-type impurities or the second conductivity-type impurities at a concentration lower than a concentration of one of the first conductivity-type impurities in the first conductivity-type layer or the second conductivity-type impurities in the second conductivity-type layer, and

the first conductivity-type layer, the intermediate layer, and the second conductivity-type layer are stacked in a thickness direction of a semiconductor substrate inside the semiconductor substrate; and

a separating layer between each of the first conductivity-type layer, the intermediate layer, and the second conductivity-type layer and the semiconductor substrate, wherein the separating layer isolates each of the first conductivity-type layer, the intermediate layer, and the second conductivity-type layer from the semiconductor substrate, wherein

a stacking body of the first conductivity-type layer, the intermediate layer, and the second conductivity-type layer penetrates through the semiconductor substrate in the thickness direction of the semiconductor substrate,

the first conductivity-type layer is exposed on a first main surface of the semiconductor substrate,

the second conductivity-type layer is exposed on a second main surface of the semiconductor substrate, and

the first main surface is opposite to the second main surface.

2. The semiconductor device according to claim 1 , wherein a cross-sectional shape of the separating layer in the thickness direction of the semiconductor substrate is tapered.

3. The semiconductor device according to claim 1 , wherein at least one of the first conductivity-type layer or the second conductivity-type layer is exposed by an opening in the semiconductor substrate.

4. The semiconductor device according to claim 1 , wherein the intermediate layer includes one of the first conductivity-type impurities or the second conductivity-type impurities at the concentration lower than the concentration of one of the first conductivity-type impurities in the first conductivity-type layer or the second conductivity-type impurities in the second conductivity-type layer.

5. The semiconductor device according to claim 1 , wherein one of the first conductivity-type layer or the second conductivity-type layer is electrically coupled to a via in a multi-layer wiring layer on a main surface of a plurality of main surfaces of the semiconductor substrate.

6. An electronic apparatus, comprising:

a semiconductor device inside a semiconductor substrate, wherein the semiconductor device comprises:

a first conductivity-type layer that comprises first conductivity-type impurities;

a second conductivity-type layer that comprises second conductivity-type impurities, wherein the second conductivity-type impurities are different in polarity from the first conductivity-type impurities;

an intermediate layer sandwiched between the first conductivity-type layer and the second conductivity-type layer, wherein

the intermediate layer does not include the first conductivity-type impurities or the second conductivity-type impurities, or includes one of the first conductivity-type impurities or the second conductivity-type impurities at a concentration lower than a concentration of one of the first conductivity-type impurities in the first conductivity-type layer or the second conductivity-type impurities in the second conductivity-type layer, and

the first conductivity-type layer, the intermediate layer, and the second conductivity-type layer are stacked in a thickness direction of a semiconductor substrate inside the semiconductor substrate; and

a separating layer between each of the first conductivity-type layer, the intermediate layer, and the second conductivity-type layer and the semiconductor substrate, wherein the separating layer isolates each of the first conductivity-type layer, the intermediate layer, and the second conductivity-type layer from the semiconductor substrate, wherein

a stacking body of the first conductivity-type layer, the intermediate layer, and the second conductivity-type layer penetrates through the semiconductor substrate in the thickness direction of the semiconductor substrate,

the first conductivity-type layer is exposed on a first main surface of the semiconductor substrate,

the second conductivity-type layer is exposed on a second main surface of the semiconductor substrate, and

the first main surface is opposite to the second main surface.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 21, 2020
From: OKANO, HITOSHI
To: SONY SEMICONDUCTOR SOLUTIONS CORPORATION
Reel/Frame 052739/0350 →
Priority Claims (1)
JP JP2017-165619 · Aug 30, 2017 · national
Continuity (1)
Related Publication 20200357933A1 · Nov 12, 2020