Printed wiring-board islands for connecting chip packages and methods of assembling same
A printed wiring-board island relieves added complexity to a printed circuit board. The printed wiring-board island creates an island form factor in the printed circuit board. Coupling of a semiconductive device package to the printed wiring-board island includes a ball-grid array. The ball-grid array can at least partially penetrate the printed wiring-board island.
1. A semiconductive device substrate, comprising:
a printed wiring-board island including a die side and a board side, wherein printed wiring-board island includes a die-side routing density on the die-side and a board-side routing density on the board-side; and
a printed circuit board onto which the printed wiring-board island is mounted, wherein the printed circuit board includes a printed circuit board routing density, wherein the printed wiring-board island board-side routing density matches the printed circuit board routing density, and wherein the printed wiring-board island creates an island form factor on the printed circuit board.
2. The semiconductive device substrate of claim 1 , further including a reflowed solder-paste printed on one of the printed wiring-board island and the printed circuit board, wherein the reflowed solder paste bonds the printed wiring-board island to the printed circuit board.
3. The semiconductive device substrate of claim 1 , further including:
a reflowed solder-paste printed on one of the printed wiring-board island and the printed circuit board, wherein the reflowed solder paste bonds the printed wiring-board island to the printed circuit board; and
a thermo-coupling, non-conductive paste also bonding the printed wiring-board island and the printed circuit board.
4. The semiconductive device substrate of claim 1 , further including a semiconductive device package disposed on the printed wiring-board island and coupled to the printed wiring-board island on the die-side by a ball-grid array, wherein the ball-grid array reflects the semiconductive-package routing density.
5. The semiconductive device substrate of claim 1 , wherein the printed wiring-board island includes trace-layer structure selected from the group consisting of a single trace layer, two trace layers, three trace layers and four trace layers.
6. The semiconductive device substrate of claim 1 , further including at least one semiconductive device package disposed on the printed wiring-board island and coupled to the printed wiring-board island and to the printed circuit board by a ball-grid array, wherein the ball-grid array at least partially penetrates the printed wiring-board island, and wherein the ball-grid array partially reflects the semiconductive-package routing density.
7. The semiconductive device substrate of claim 6 , further including a bump pad embedded within the printed wiring-board island at a trace level, wherein a ball from the ball-grid array contacts the bump pad.
8. The semiconductive device substrate of claim 7 , further including a bump pad embedded within the printed wiring-board island at a trace level, wherein a ball from the ball-grid array contacts and passes through a mesh structure of the bump pad.
9. The semiconductive device substrate of claim 6 , wherein the printed wiring-board island includes trace-layer structure selected from the group consisting of a single trace layer, two trace layers, three trace layers and four trace layers.
10. The semiconductive device substrate of claim 7 , further including a solder-paste printed bump in contact with the bump pad at a board side of the printed wiring-board island.
11. The semiconductive device substrate of claim 6 , further including a bump pad embedded within the printed wiring-board island at a trace level, wherein the bump pad has a mesh form factor.
12. The semiconductive device substrate of claim 1 , further including a semiconductive device package disposed on the printed wiring-board island and coupled to the printed wiring-board island on the die-side by a ball-grid array, wherein the ball-grid array reflects the semiconductive-package routing density, wherein the semiconductive device package includes a core processor, a baseband processor, a memory module and at least one of a memory-controller hub and a platform-controller hub.
13. The semiconductive device substrate of claim 12 , further including a bump pad embedded within the printed wiring-board island at a trace level, wherein a ball from the ball-grid array contacts the bump pad.
14. The semiconductive device substrate of claim 12 , further including a bump pad embedded within the printed wiring-board island at a trace level, wherein a ball from the ball-grid array contacts and passes through a mesh structure of the bump pad.
15. The semiconductive device substrate of claim 13 , further including:
a reflowed solder-paste printed on one of the printed wiring-board island and the printed circuit board, wherein the reflowed solder paste bonds the printed wiring-board island to the printed circuit board; and
a thermo-coupling, non-conductive paste also bonding the printed wiring-board island and the printed circuit board.
16. A computing system, comprising:
a printed wiring-board island including a semiconductive-package routing density on a die-side thereof and a printed circuit board routing density on a board-side thereof;
a printed circuit board onto which the printed wiring-board is mounted, wherein the printed circuit board includes the printed circuit board routing density, and wherein the printed wiring-board island creates an island form factor on the printed circuit board;
a semiconductive device package disposed on the printed wiring-board island and coupled to the printed wiring-board island by a ball-grid array, wherein the ball-grid array includes the semiconductive-package routing density; and
an outer shell covering the semiconductive device package, the printed wiring-board island and the printed circuit board.
17. The computing system of claim 16 , wherein the ball-grid array at least partially penetrates the printed wiring-board island, and wherein the ball-grid array includes the semiconductive-package routing density.
18. A semiconductive device substrate, comprising:
a printed wiring-board island including a die side and a board side, wherein printed wiring-board island includes a die-side routing density on the die-side and a board-side routing density on the board-side;
a printed circuit board onto which the printed wiring board island is mounted, wherein the printed circuit board includes a printed circuit board routing density, wherein the printed wiring-board island board-side routing density matches the printed circuit board routing density, and wherein the printed wiring-board island creates an island form factor on the printed circuit board;
a reflowed solder-paste printed on one of the printed wiring-board island and the printed circuit board, wherein the reflowed solder paste bonds the printed wiring-board island to the printed circuit board; and
a thermo-coupling, non-conductive paste also bonding the printed wiring-board island and the printed circuit board.
19. The semiconductive device substrate of claim 18 , wherein the printed wiring-board island includes trace-layer structure selected from the group consisting of a single trace layer, two trace layers, three trace layers and four trace layers.
20. The semiconductive device substrate of claim 19 , further including a semiconductive device package disposed on the printed wiring-board island and coupled to the printed wiring-board island on the die-side by a ball-grid array, wherein the ball-grid array at least partially penetrates the printed wiring-board island wherein the ball-grid array reflects the semiconductive-package routing density.
21. The semiconductive device substrate of claim 19 , further including a semiconductive device package disposed on the printed wiring-board island and coupled to the printed wiring-board island on the die-side by a ball-grid array, wherein the ball-grid array reflects the semiconductive-package routing density, wherein the semiconductive device package includes a core processor, a baseband processor, a memory module and at least one of a memory-controller hub and a platform-controller hub.
22. The semiconductive device substrate of claim 19 , further including:
a semiconductive device package disposed on the printed wiring-board island and coupled to the printed wiring-board island on the die-side by a ball-grid array, wherein the ball-grid array at least partially penetrates the printed wiring-board island wherein the ball-grid array reflects the semiconductive-package routing density; and
a bump pad embedded within the printed wiring-board island at a trace level, wherein a ball from the ball-grid array contacts and passes through a mesh structure of the bump pad.
23. The semiconductive device substrate of claim 22 , further including the semiconductive device package includes a core processor, a baseband processor, a memory module and at least one of a memory-controller hub and a platform-controller hub.