Group III-Nitride devices on SOI substrates having a compliant layer
A semiconductor-on-insulator (SOI) substrate with a compliant substrate layer advantageous for seeding an epitaxial III-N semiconductor stack upon which III-N devices (e.g., III-N HFETs) may be formed. The compliant layer may be (111) silicon, for example. The SOI substrate may further include another layer that may have one or more of lower electrical resistivity, greater thickness, or a different crystal orientation relative to the compliant substrate layer. A SOI substrate may include a (100) silicon layer advantageous for integrating Group IV devices (e.g., Si FETs), for example. To reduce parasitic coupling between an HFET and a substrate layer of relatively low electrical resistivity, one or more layers of the substrate may be removed within a region below the HFETs. Once removed, the resulting void may be backfilled with another material, or the void may be sealed, for example during back-end-of-line processing.
1. An integrated circuit (IC) structure, comprising:
a first substrate layer comprising (111) silicon;
a first dielectric material in direct contact with the first substrate layer;
a first Group III-Nitride (III-N) material within an opening in the first dielectric material, where the first Group III-N material has a c-axis substantially orthogonal to a (111) plane of the first substrate layer;
a second dielectric material between the first substrate layer and an underlying second substrate layer comprising crystalline silicon;
a void, or a material of lower relative permittivity than that of the second dielectric material, between the first Group III-N material and the second substrate layer, co-planar with the second dielectric material, and co-linear with the c-axis; and
a transistor comprising a second Group III-N material, wherein the second Group III-N material is epitaxial to the first Group III-N material.
2. The IC structure of claim 1 , wherein:
the first substrate layer has a thickness no more than 100 nm;
the second substrate layer has a lower electrical resistivity than the first substrate layer; and
the first dielectric material has a thickness greater than that of the first substrate layer.
3. The IC structure of claim 2 , wherein:
the transistor is a first transistor;
the second substrate layer comprises (100) silicon;
the first Group III-N material is in direct contact with the first substrate layer within a first region of the IC structure;
a second transistor comprising a Group IV material is above the second substrate layer within a second region of the IC structure; and
one or more metallization levels electrically couples the first transistor to the second transistor.
4. The IC structure of claim 3 , wherein:
the transistor comprises a III-N heterostructure field effect transistor (HFET); and
the second transistor comprises a metal-oxide-semiconductor (MOS)FET.
5. The IC structure of claim 1 , wherein:
the second dielectric material comprises silicon and oxygen; and
the first substrate layer has a thickness no more than 50 nm.
6. The IC structure of claim 1 , wherein the void is between the first substrate layer and the second substrate layer where the second dielectric material is absent.
7. The IC structure of claim 6 , further comprising:
a non-conductive via that intersects the void, and extends through at least one of the first dielectric material or the first Group III-N material.
8. The IC structure of claim 1 , wherein a portion of the first substrate layer co-linear with the c-axis is also absent.
9. The IC structure of claim 1 , wherein:
the second Group III-N material is between the first Group III-N material and a Group III-N polarization layer that is on a c-plane of the second Group III-N material, the second Group III-N material having a thickness of at least 1 μm; and
the Group III-N polarization layer has a composition that induces a 2D electron gas in a channel region of the second Group III-N material.
10. The IC structure of claim 1 , further comprising one or more metallization levels, wherein the one or more metallization levels further comprise:
a plurality of first metallization levels over first gate electrodes and first source/drain terminals within a first region of the IC;
a plurality of second metallization levels over second gate electrodes and second source/drain terminals within a second region of the IC; and
a third metallization level over both the first metallization levels and the second metallization levels, the third metallization level interconnecting at least an uppermost one of the first metallization levels with the second metallization levels.
11. A system-on-chip (SOC), comprising:
RF circuitry comprising the IC structure of claim 1 ; and
processor circuitry coupled to the RF circuitry, wherein the processor circuitry comprises one or more metal-oxide-semiconductor (MOSFETs) including (100) silicon within a second region of the IC structure that lacks the first substrate layer.
12. The SOC of claim 11 , wherein:
the IC structure further comprises a gate electrode over a (0001) surface of the second Group III-N material;
the second substrate layer has a lower electrical resistivity than the first substrate layer;
the first substrate layer has a thickness less than 100 nm; and
the second dielectric material comprises silicon and oxygen and has a thickness of at least 500 nm.
13. The SOC of claim 11 , wherein the void is present between the transistor and the second substrate layer, and within the void one or more of:
the second dielectric material is absent;
the first substrate layer is absent; or
the second substrate layer is recessed relative to other portions of the second substrate layer.
14. An integrated circuit (IC) structure, comprising:
a first substrate layer comprising (111) silicon over a second substrate layer also comprising silicon within a region of the IC structure, wherein the first substrate layer is separated from the second substrate layer by a layer of substrate dielectric material; and
a device comprising a Group III-Nitride (III-N) material above the first substrate layer within the region of the IC structure, wherein the substrate dielectric material is absent within at least a portion of the region that is below the device, and wherein the device comprises a III-N heterostructure field effect transistor (HFET); and
a second device comprising a Group IV material above the second substrate layer within a second region of the IC structure, wherein:
the second device comprises a metal-oxide-semiconductor (MOS)FET;
the MOSFET is on a surface of raised (100) silicon in contact with the second substrate layer; and
an isolation dielectric surrounds the Group III-N material, laterally separating the Group III-N material from the raised (100) silicon.