Data transmission device including shared memory having exclusive bank memories for writing and reading

1. A data transmission device for in-vehicle multi-core control that includes M (M is an integer of 2 or more) bank memories and N (N is an integer of 2 or more) processors configured to access the M bank memories, the device comprising:

a shared memory on which the M bank memories are arranged and which is accessible by the N processors; and

an access control circuit that controls access to the M bank memories by the N processors based on identification information for specifying the M bank memories, wherein:

the access control circuit:

assigns only one processor used for writing to a bank memory, of the M bank memories, in which writing is performed,

assigns K (K is an integer of 1 or more and N−1 or less) processors used for reading from a bank memory, of the M bank memories, in which reading is performed, and

exclusively controls bank memory access such that the bank memory in which the writing is performed and the bank memory in which the reading is performed are not the same, and

contents of a bank memory in which writing was last performed are copied to the bank memory in which the writing is performed by the only one processor before the access control circuit assigns the only one processor.

2. The data transmission device for in-vehicle multi-core control according to claim 1 , wherein the access control circuit returns the identification information of the bank memory in which writing was last performed when the reading is performed, and returns the identification information of a given bank memory, other than the bank memory in which writing was last performed.

3. The data transmission device for in-vehicle multi-core control according to claim 1 , wherein a number of processors used for writing is set as 1, K is set as N−1, and M is set as N+1.

4. The data transmission device for in-vehicle multi-core control according to claim 1 , further comprising:

N scratchpad memories each obtained by grouping the M bank memories,

wherein N processors are used for writing and are in one-to-one correspondence with the N scratchpad memories.

5. The data transmission device for in-vehicle multi-core control according to claim 4 , wherein execution codes for realizing a write operation and a read operation performed for the N scratchpad memories and functions including the execution codes are retained in an execution code storage region locally provided for each processor.

6. The data transmission device for in-vehicle multi-core control according to claim 5 , wherein only a write code and a write function are implemented for the only one processor used for writing which corresponds to a first of the N scratchpad memories, and only a read code and a read function are implemented for the K processors used for reading which correspond to a second of the N scratchpad memories.

7. The data transmission device for in-vehicle multi-core control according to claim 1 , further comprising:

a counter array region, a first register, and a second register arranged in the shared memory,

wherein the counter array region stores a number of times of accessing the M bank memories by the K processors,

the first register stores identification information for specifying the bank memory in which writing was last performed,

the second register stores identification information for specifying a different bank memory than the bank memory in which writing was last performed, and

the access control circuit controls access to the M bank memories based on the number of times of accessing stored in the counter array region, the identification information stored in the first register, and the identification information stored in the second register.

8. A data transmission method comprising:

providing a device for in-vehicle multi-core control that includes M (M is an integer of 2 or more) bank memories and N (N is an integer of 2 or more) processors accessible to the M bank memories;

arranging the M bank memories on a shared memory which is accessible by the N processors;

controlling, using an access control circuit, access to the M bank memories by the N processors based on identification information for specifying the M bank memories;

assigning only one processor used for writing to a bank memory, of the M bank memories, in which writing is performed;

assigning K (K is an integer of 1 or more and N−1 or less) processors used for reading from a bank memory, of the M bank memories, in which reading is performed,

exclusively controlling bank memory access such that the bank memory in which the writing is performed and the bank memory in which the reading is performed are not the same, and

copying contents of a bank memory in which writing was last performed to the bank memory in which the writing is performed by the only one processor before the access control circuit assigns the only one processor.