IP Library Granted Patent US 11,265,112
Granted Patent B2
US 11,265,112 · App. 16/649,993 · Granted Mar 1, 2022

Enhanced polling procedures

Inventors: Magnus Nilsson (Umea, SE); Marcin Potorski (Szczecin, PL); Jose Cesares Cano (Munich, DE)
Assignee: INTEL CORPORATION
H04L1/1685H04W76/25H04W80/02H04W80/08
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Quick Facts
Patent No.
US 11,265,112
App. No.
16/649,993
Granted
Mar 1, 2022
Kind
B2
Abstract

A device for wireless communications includes one or more protocol processors for executing a protocol stack, the one or more protocol processors configured to generate a first RLC (Radio Link Control) PDU (Protocol Data Unit) with data from a first upper-layer PDU and transmit the first RLC PDU to a counterpart base station RLC, generate a second RLC PDU, with its poll bit set, with data from a second upper-layer PDU and transmit the second RLC PDU to the counterpart base station RLC, and receive a status PDU from the counterpart base station RLC that indicates a status of the first and second RLC PDUs.

Claims (38)

1. A device for wireless communications comprising one or more processors configured to:

generate a first RLC (Radio Link Control) PDU (Protocol Data Unit) with data from a first upper-layer PDU and transmit the first RLC PDU to a counterpart base station RLC;

generate a second RLC PDU, with its poll bit set to indicate to the counterpart base station RLC that the second RLC PDU is a final RLC PDU of a plurality of RLC PDUs comprising the first RLC PDU and the second RLC PDU, with data from a second upper-layer PDU and transmit the second RLC PDU to the counterpart base station RLC;

receive a status PDU from the counterpart base station RLC that indicates a status of the first RLC PDU and the second RLC PDU in response to the counterpart base station RLC receiving the second RLC PDU; and

report the status of the first and second upper-layer PDUs to an upper-layer that provided them based on the status PDU.

2. The device of claim 1 , comprising a digital signal processor configured to perform PHY (physical layer) functions.

3. The device of claim 1 , further comprising an interface to communicate with a radio frequency transceiver of a terminal device.

4. The device of claim 1 , wherein the first RLC PDU does not have its poll bit set.

5. The device of claim 1 , wherein the first and second upper-layer PDUs are NAS (Non-Access Stratum) PDUs.

6. The device of claim 1 , wherein the first and second upper-layer PDUs are control plane signaling PDUs that comprise user plane data.

7. The device of claim 1 , wherein the one or more processors are further configured to:

determine whether an upper-layer that provided the first and second upper-layer PDUs has pending data; and

determine to set the poll bit of the second RLC PDU based on the upper-layer not having pending data.

8. The device of claim 1 , wherein the one or more processors are further configured to:

track a number of monitored PDUs that have been transmitted since a previous RLC polling was performed; and

determine to set the poll bit of the second RLC PDU based on the number of monitored PDUs reaching a predefined quantity of monitored PDUs.

9. The device of claim 1 , wherein the one or more processors are further configured to:

before generating and transmitting the first RLC PDU, generate and transmit one or more additional RLC PDUs without set poll bits, wherein the status PDU also indicates a status of the one or more additional RLC PDUs.

10. The device of claim 1 , wherein the one or more processors are further configured to:

generate and transmit RLC PDUs for a continuous sequence of upper-layer PDUs until an upper-layer indicates that it has no pending data, where the second upper-layer PDU is the final upper-layer PDU in the continuous sequence of upper-layer PDUs.

11. The device of claim 1 , wherein the one or more processors are further configured to:

track a number of monitored PDUs; and

generate and transmit RLC PDUs until the number of monitored PDUs has reached a predefined quantity of monitored PDUs.

12. A device for wireless communications comprising one or more processors configured to:

receive data of a first upper-layer data unit and data of a second upper-layer data unit at a polling entity of a protocol stack;

generate a first data unit with the data of the first upper-layer data unit and transmit the first data unit to a counterpart polling entity;

generate a second data unit, with its poll bit set, with the data of the second upper-layer data unit and transmit the second data unit to the counterpart polling entity;

receive a status data unit from the counterpart polling entity that indicates a status of the first data unit and the second data unit; and

report the status of the first and second upper-layer data units to an upper-layer that provided them based on the status data unit.

13. The device of claim 12 , comprising a digital signal processor configured to perform PHY (physical layer) functions.

14. The device of claim 12 , further comprising an interface to communicate with a radio frequency transceiver of a terminal device.

15. The device of claim 12 , wherein the first data unit does not have a set poll bit.

16. A method of performing wireless communications, the method comprising:

generating a first RLC (Radio Link Control) PDU (Protocol Data Unit) with data from a first upper-layer PDU and transmitting the first RLC PDU to a counterpart base station RLC;

generating a second RLC PDU, with its poll bit set, with data from a second upper-layer PDU and transmitting the second RLC PDU to the counterpart base station RLC;

receiving a status PDU from the counterpart base station RLC that indicates a status of the first RLC PDU and the second RLC PDU; and

reporting the status of the first and second upper-layer PDUs to an upper-layer that provided them based on the status PDU.

17. The method of claim 16 , wherein the first RLC PDU does not have its poll bit set.

Assignments (3)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 22, 2021
From: INTEL IP CORPORATION
To: INTEL CORPORATION
Reel/Frame 056337/0609 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 21, 2020
From: POTORSKI, MARCIN; CESARES CANO, JOSE
To: INTEL IP CORPORATION
Reel/Frame 053573/0893 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 21, 2020
From: NILSSON, MAGNUS
To: INTEL IP CORPORATION
Reel/Frame 053573/0924 →