Method for porosifying a material and semiconductor structure
A method for porosifying a Ill-nitride material in a semiconductor structure is provided, the semiconductor structure comprising a sub-surface structure of a first Ill-nitride material, having a charge carrier density greater than 5×10 17 cm −3 , beneath a surface layer of a second Ill-nitride material, having a charge carrier density of between 1×10 14 cm −3 and 1×10 17 cm −3 . The method comprises the steps of exposing the surface layer to an electrolyte, and applying a potential difference between the first Ill-nitride material and the electrolyte, so that the sub-surface structure is porosified by electrochemical etching, while the surface layer is not porosified. A semiconductor structure and uses thereof are further provided.
1. A method for porosifying a III-nitride material in a semiconductor structure comprising a sub-surface structure of a first III-nitride material, having a charge carrier density greater than 5×10 17 cm −3 , beneath a surface layer of a second III-nitride material, having a charge carrier density of between 1×10 14 cm −3 and 1×10 17 cm −3 , the method comprising the steps of:
exposing the surface layer to an electrolyte; and
applying a potential difference between the first III-nitride material and the electrolyte, so that the sub-surface structure is porosified by electrochemical etching through the surface layer, while the surface layer is not porosified.
2. A method according to claim 1 , in which the semiconductor structure is not pre-patterned with trenches separated by less than 1 cm, or 5 mm, or 1 mm, or 600 μm, or 400 μm, or 200 μm, and in which the surface layer is not coated with an electrically insulating layer or other protective layer during electrochemical etching.
3. A method according to claim 1 , in which the charge carrier density in the sub-surface structure is at least 5 times, or 10 times, or 100 times, or 1000 times, or 10,000 times, or 100,000 times, or 1,000,000 times higher than the charge carrier density in the surface layer.
4. A method according to claim 1 , in which the threading dislocation density in both the surface layer and the sub-surface structure is at least 1×10 4 cm −2 , 1×10 5 cm −2 , 1×10 6 cm −2 , 1×10 7 cm −2 , or 1×10 8 cm −2 and/or less than 1×10 9 cm −2 or 1×10 10 cm −2 .
5. A method according to claim 1 , in which the surface layer and the sub-surface structure comprise III-nitride materials selected from the list consisting of: GaN, AlGaN, InGaN, InAlN and AlInGaN.
6. A method according to claim 1 , in which the thickness of the surface layer is at least 1 nm, or 10 nm, or 100 nm, and/or less than 1 μm, or 5 μm, or 10 μm.
7. A method according to claim 1 , in which an outer surface of the surface layer has a minimum lateral dimension of at least 300 μm, or at least 500 μm, or at least 1 mm, or at least 10 mm, or at least 5 cm, or at least 15 cm, or at least 20 cm, and/or in which the sub-surface structure has a minimum lateral dimension of at least 300 μm, or at least 500 μm, or at least 1 mm, or at least 10 mm, or at least 5 centimetres.
8. A method according to claim 7 , in which the semiconductor structure is a wafer with a diameter of 1 inch (2.54 cm), or 2 inches (5.08 cm), or 6 inches (15.24 cm), or 8 inches (20.36 cm).
9. A method according to claim 1 , in which semiconductor structure comprises a plurality of the sub-surface structures which form a plurality of sub-surface layers arranged in a stack, and in which the sub-surface layers are sequentially etched from the surface layer down.
10. A method according to claim 9 , comprising the step of controlling the porosity of a selected sub-surface layer by controlling the potential difference between the electrolyte and the selected sub-surface layer during electrochemical etching.