Gateway device
Provided is a gateway device capable of reducing power consumption in a sleep state and relaying an activation signal between networks without delay. When receiving an activation signal, the gateway device according to the present invention transfers the activation signal to another network via a relay switch, and outputs a signal indicating the reception of the activation signal from a transceiver, thereby turning on a microcomputer.
1. A gateway device that relays communication between a first network and a second network, the device comprising:
a first transceiver that transmits and receives signals to and from the first network;
a second transceiver that transmits and receives signals to and from the second network;
a relay switch that relays communication;
an arithmetic device that relays communication between the first network and the second network via the first transceiver and the second transceiver; and
a power supply circuit that supplies power to the arithmetic device, wherein
both the first transceiver and the second transceiver are configured to be able to switch between a first mode for transmitting and receiving signals and a second mode having lower power consumption than the first mode,
when an instruction is output to switch the first transceiver and the second transceiver from the first mode to the second mode, the arithmetic device outputs the instruction and turns off the power supply circuit to block power supply to the arithmetic device,
the first transceiver, when operating in the second mode, is configured to be able to receive an activation instruction signal instructing to activate the gateway device from the first network and shift to the first mode,
the second transceiver, when operating in the second mode, is configured to be able to receive the activation instruction signal from the second network and shift to the first mode,
when the first transceiver and the second transceiver operate in the second mode, the gateway device turns on the relay switch to relay the activation instruction signal between the first network and the second network without interposing the arithmetic device,
the first transceiver, when receiving the activation instruction signal, is configured to output a first activation instruction detection signal indicating the reception to the second transceiver,
the second transceiver, when receiving the activation instruction signal, is configured to output a second activation instruction detection signal indicating the reception to the first transceiver,
the power supply circuit is configured to supply power to the arithmetic device according to at least one of a case where the first transceiver outputs the first activation instruction detection signal or a case where the second transceiver outputs the second activation instruction detection signal, and
a delay circuit configured to turn off the relay switch after a delay of a predetermined delay time with at least one of a time when the first transceiver outputs the first activation instruction detection signal or a time when the second transceiver outputs the second activation instruction detection signal as a starting point,
wherein the delay time is set to be equal to or longer than at least a time from when the first transceiver shifts from the second mode to the first mode to when the first transceiver finishes relaying the activation instruction signal to the second transceiver through the relay switch, and
wherein the delay time is set to be equal to or longer than at least a time from when the second transceiver shifts from the second mode to the first mode to when the second transceiver finishes relaying the activation instruction signal to the first transceiver through the relay switch.
2. The gateway device according to claim 1 , further comprising:
an OR circuit, wherein
the OR circuit is configured to output a signal instructing that the power supply circuit supplies power to the arithmetic device while receiving at least one of the first activation instruction detection signal, the second activation instruction detection signal, and a signal output by the arithmetic device and indicating that the arithmetic device is operating, and
when switching the first transceiver and the second transceiver from the first mode to the second mode, the arithmetic device outputs a signal indicating the switch to the first transceiver and the second transceiver and outputs a signal indicating that the arithmetic device is not operating to the OR circuit.
3. The gateway device according to claim 1 , wherein
the first transceiver includes a first sleep input terminal that receives a signal instructing the first transceiver to switch between operations in the first mode and the second mode, and
the second transceiver includes a second sleep input terminal that receives a signal instructing the second transceiver to switch between the operations in the first mode and the second mode,
the gateway device further comprising:
a first switch that switches a signal input to the first sleep input terminal between the first activation instruction detection signal and a signal output by the arithmetic device; and
a second switch that switches a signal input to the second sleep input terminal between the second activation instruction detection signal and a signal output by the arithmetic device, wherein
when the first transceiver and the second transceiver shift to the second mode, the arithmetic device outputs a sleep signal indicating the shift via the first sleep input terminal and the second sleep input terminal, and
after outputting the sleep signal, the arithmetic device switches the first switch so that the second activation instruction detection signal is input to the first sleep input terminal, and switches the second switch so that the first activation instruction detection signal is input to the second sleep input terminal.
4. The gateway device according to claim 1 , wherein
the first transceiver includes a first sleep input terminal that receives a signal instructing the first transceiver to switch between operations in the first mode and the second mode, and
the second transceiver includes a second sleep input terminal that receives a signal instructing the second transceiver to switch between the operations in the first mode and the second mode,
the gateway device further comprising:
a first switch that switches a signal input to the first sleep input terminal between the first activation instruction detection signal and a signal output by the arithmetic device; and
a second switch that switches a signal input to the second sleep input terminal between the second activation instruction detection signal and a signal output by the arithmetic device, wherein
when the arithmetic device is activated by receiving power from the power supply circuit, the arithmetic device switches the first switch so as to input a signal output by the arithmetic device to the first sleep input terminal, and switches the second switch so as to input a signal output by the arithmetic device to the second sleep input terminal.
5. The gateway device according to claim 1 , wherein
the arithmetic device turns off the relay switch while receiving power supply from the power supply circuit.
6. The gateway device according to claim 1 , wherein
the relay switch is arranged at a position bypassing between a signal line connecting the first network and the first transceiver and a signal line connecting the second network and the second transceiver,
when the first transceiver and the second transceiver operate in the second mode, the gateway device relays communication between the first network and the second network without interposing the first transceiver, the second transceiver, and the arithmetic device by turning on the relay switch, and
when the first transceiver and the second transceiver operate in the first mode, the gateway device relays communication between the first network and the second network through the first transceiver, the second transceiver, and the arithmetic device by turning off the relay switch.